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Inexact floating-point adder for dynamic image processing

机译：用于动态图像处理的不精确浮点加法器

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Power has become a key constraint in current nanoscale integrated circuit design due to the increasing demands for mobile computing and a low carbon economy. As an emerging technology, an inexact circuit design offers a promising approach to significantly reduce both dynamic and static power dissipation for error tolerant applications. Although fixed-point arithmetic circuits have been studied in terms of inexact computing, floating-point arithmetic circuits have not been fully considered although require more power. In this paper, the first inexact floating-point adder is designed and applied to high dynamic range (HDR) image processing. Inexact floating-point adders are proposed by approximately designing an exponent subtractor and mantissa adder. Related logic operations including normalization and rounding modules are also considered in terms of inexact computing. Two HDR images are processed using the proposed inexact floating-point adders to show the validity of the inexact design. HDR-VDP is used as a metric to measure the subjective results of the image addition. Significant improvements have been achieved in terms of area, delay and power consumption. Comparison results show that the proposed inexact floating-point adders can improve power consumption and the power-delay product by 29.98% and 39.60%, respectively.
机译：由于对移动计算的需求不断增加以及低碳经济，功率已成为当前纳米级集成电路设计中的关键约束。作为一种新兴技术，不精确的电路设计提供了一种有前途的方法，可以显着降低用于容错应用的动态和静态功耗。尽管已经就不精确计算方面研究了定点算术电路，但是尽管需要更多的功率，但尚未完全考虑浮点算术电路。本文设计了第一个不精确的浮点加法器，并将其应用于高动态范围（HDR）图像处理。通过近似设计指数减法器和尾数加法器，提出了不精确的浮点加法器。不精确计算也考虑了包括归一化和舍入模块在内的相关逻辑运算。使用建议的不精确浮点加法器处理了两个HDR图像，以显示不精确设计的有效性。 HDR-VDP用作度量图像添加的主观结果的度量。在面积，延迟和功耗方面都取得了显着改善。比较结果表明，所提出的不精确浮点加法器可以分别将功耗和功率延迟乘积分别提高29.98％和39.60％。

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