• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>IEEE Electronics Packaging Technology Conference >Structure reliability and characterization for FC package w/Embedded Trace coreless Substrate
【24h】

Structure reliability and characterization for FC package w/Embedded Trace coreless Substrate

机译：带嵌入式迹线无芯基板的FC封装的结构可靠性和特性

获取原文
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

In recent years mobile devices are getting more and more involved in to our daily life. With the requirement of IC packages inside mobile devices toward smaller form factor, low cost with high performance, a coreless substrate technology, naming Embedded Trace Substrate (ETS) is developed to meet market requirement and it has been studied in this paper. For an IC package with coreless substrate, warpage performance is a concern comparing to non-coreless substrate package of which has better substrate strength to balance Coefficients of Thermal Expansion (CTE) mismatch from molding compound. A Flip Chip Chip Scale Package (FCCSP) with body size 12×12mm is used as a test vehicle for this study and molding underfill (MUF) structure is selected to reduce package cost of additional underfill material. To evaluate the warpage performance of the ETS coreless substrate, finite element analysis simulation tool is used to compare package warpage for room temperature and high temperature. Also experimental validation of warpage is done by Shadow Moire test equipment. The study matrix includes different molding compound materials, molding compound thicknesses, substrate designs, substrate thicknesses, die thicknesses. By simulation and Shadow Moire measurement results can help the package structure and molding compound material selection that with thicker molding compound thickness, die thickness and substrate thickness have better warpage performance. In addition to warpage, the reliability performance is also evaluated for package under different test conditions such as assembly out time zero, uHAST, TCT and HTST. The evaluation index is Open/Short yield and failure analysis is also done for the O/S failed samples to evaluate failure rate, failure mode and failure locations. In the end, a package structure and bill of material (BOM) selection is finalized to have suitable warpage performance that meets requirement and can also pass reliability criteria.
机译：近年来，移动设备越来越多地参与到我们的日常生活中。随着移动设备内部IC封装对更小尺寸，低成本，高性能的要求，开发了一种无核衬底技术，即命名嵌入式跟踪衬底（ETS）以满足市场需求，并且本文已对此进行了研究。对于具有无芯基板的IC封装，与具有更好的基板强度以平衡模塑料的热膨胀系数（CTE）不匹配的非无芯基板封装相比，翘曲性能是一个值得关注的问题。这项研究的测试工具是采用尺寸为12×12mm的倒装芯片尺寸封装（FCCSP），并选择模制底部填充（MUF）结构以降低其他底部填充材料的包装成本。为了评估ETS无芯基板的翘曲性能，使用有限元分析仿真工具比较了室温和高温下的封装翘曲。阴影变形测试设备也可以进行翘曲的实验验证。研究矩阵包括不同的模塑料材料，模塑料厚度，基板设计，基板厚度，模具厚度。通过仿真和Shadow Moire测量结果可以帮助封装结构和模塑料材料的选择，其中模塑料厚度越厚，模具厚度和基板厚度具有更好的翘曲性能。除了翘曲以外，还评估了在不同测试条件下的封装可靠性性能，例如零组装时间，uHAST，TCT和HTST。评估指标为开放/空头屈服，并且还对操作系统失败的样本进行了失败分析，以评估失败率，失败模式和失败位置。最后，封装结构和材料清单（BOM）的选择最终确定为具有合适的翘曲性能，既可以满足要求，也可以通过可靠性标准。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号