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A low-resource 32-bit datapath ECDSA design for embedded applications

机译：适用于嵌入式应用程序的低资源32位数据路径ECDSA设计

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In this paper we describe a hardware implementation of a low resource digital signature design using Elliptic Curve Digital Signature Algorithm (ECDSA). The implementation of ECDSA is based on the recommended GF (2) NIST Elliptic Curve Cryptography (ECC). Elliptic curve based systems can be implemented with much smaller parameters, leading to significant performance advantages. Such performance improvements are particularly important for embedded applications where computing power, memory, and battery life of devices are more constrained. In order to meet these fierce constraints, our design has a 32bit word size. The design flow starts from an architectural description at the RTL level in order to interact easily with current commercial hardware synthesis tools. After simulation and synthesis steps, implementation is achieved on a Virtex-5 XC5FX70t FPGA using Xilinx's ISE design suite. Furthermore, the design was also implemented in both 65 nm and 40 nm CMOS ASIC design for performance comparisons. The Virtex-5 design requires 10838 slices with 1.58 ms (207.097 MHz) for signature generation and 12922 slices with 1.953 ms (195.309 MHz) for verification process. The ASIC design has an area of 467617 μm2 (726798 μm2) for signature generation and 260713μm2 (408350 μm2) for signature verification respectively using CMOS 65 nm and 40 nm technology. When running at a frequency of 500 MHz, the design consumes 2.71 mW (1.56 mW) of power for generation process and 3.90 mW (2.23 mW) for verification using a CMOS 65 nm and 40 nm technology respectively. From the implementation results, it is verified that the proposed ECDSA design are faster compared to literature with less power dissipation.
机译：在本文中，我们描述了使用椭圆曲线数字签名算法（ECDSA）的低资源数字签名设计的硬件实现。 ECDSA的实施基于推荐的GF（2）NIST椭圆曲线密码术（ECC）。基于椭圆曲线的系统可以使用更小的参数来实现，从而带来显着的性能优势。对于其中计算能力，内存和设备电池寿命受到更多限制的嵌入式应用程序而言，这种性能改进特别重要。为了满足这些严格的限制，我们的设计具有32位的字长。设计流程从RTL级别的体系结构描述开始，以便与当前的商用硬件综合工具轻松交互。经过仿真和综合步骤后，使用Xilinx的ISE设计套件在Virtex-5 XC5FX70t FPGA上实现了实现。此外，该设计还采用65 nm和40 nm CMOS ASIC设计进行了性能比较。 Virtex-5设计需要10838条带1.58 ms（207.097 MHz）的片来生成签名，并需要12922条带1.953 ms（195.309 MHz）的片来进行验证。 ASIC设计的面积为467617μm2（726798μm2），用于签名生成，面积为260713μm2（408350μm2），用于分别使用CMOS 65 nm和40 nm技术进行签名验证。当以500 MHz的频率运行时，该设计消耗的发电过程功耗为2.71 mW（1.56 mW），使用CMOS 65 nm和40 nm技术进行验证时分别消耗3.90 mW（2.23 mW）。从实现结果可以证明，与文献中的功耗相比，所提出的ECDSA设计比文献中的设计更快。

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