In this paper a parallel hardware structure of ASIC for HEVC intra prediction encoding is proposed. This structure by analyzing software algorithm, according to the characteristics of the ASIC implementation of parallelization, designs the DC, a planar, horizontal and vertical Angle prediction hardware structure of the parallel processing, and finished the calculation of SATD. A parallel prediction hardware structure is designed in order to improve the computational efficiency. SATD calculated using a set of registers in the shift and 4-2 compression method implements the pipeline of processing, greatly improving the throughput rate and computational efficiency. After logic synthesis using the SMIC0.13μm standard cell library, simulation results show that the proposed architecture of 4×4 logic gates for 29.8K, on-chip cache to 6.8 KB. At 300MHz, real-time processing 3840×2160@25fps sequence of images, extremely suit for VLSI HD encoder.
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