Electrical performance of dense and isolated n-type FinFETs in micro-loading effect

机译：致密和隔离n型FinFET在微负载效应下的电性能

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The micro-loading effect in this work seems obviously. According to the extraction of drive current (I) for dense and isolated FinFET devices at the on-drawn layout (W/L=0.11/0.5 (μm/μm), the ratio with 11-fin fingers vs. single fin was 10.01. Using the re-work concept to derive the un-etching depth (ΔH) located at the inner sidewall fin height was still around 2.4 nm as the outer sidewall height (H) was 90 nm.

机译：这项工作中的微加载效果似乎很明显。根据在绘制时的布局（W / L = 0.11 / 0.5（μm/μm））下密集且隔离的FinFET器件的驱动电流（I）的提取，使用11鳍状指状物与单个鳍状构件的比率为10.01。使用返工概念得出位于内侧壁鳍片高度处的未蚀刻深度（ΔH）仍约为2.4 nm，因为外侧壁高度（H）为90 nm。

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《International Symposium on Next-Generation Electronics》|2015年|1-2|共2页
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Mu-Chun Wang; Jian-Liang Lin; De-Huang Jhuang; Wen-Shiang Liao; Yi-De Lai; Wen-How Lan; Shea-Jue Wang;
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FinFET; dense; drive current; isolated; micro-loading; swing;

机译：FinFET;致密;驱动电流;隔离;微负载;摆动;

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1. The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances [J] . Kim J., Kim G., Nam H., Electron Device Letters, IEEE . 2014,第12期

机译：金属界面层-半导体源极/漏极结构对低于10nm n型Ge FinFET性能的影响
2. Electrical Characteristics of n-Type FinFETs Under $V_{T}$ Ion Implantation on SOI Substrate [J] . Shen Tien-Szu, Chou Ching-Chuan, Wang Mu-Chun, IEEE Transactions on Plasma Science . 2019,第2期

机译：在SOI衬底上离子注入下 $ V_ {T} $ 的n型FinFET的电学特性
3. Performance of Inversion, Accumulation, and Junctionless Mode n-Type and p-Type Bulk Silicon FinFETs With 3-nm Gate Length [J] . Thirunavukkarasu Vasanthan, Jhan Yi-Ruei, Liu Yan-Bo, Electron Device Letters, IEEE . 2015,第7期

机译：栅极长度为3nm的反相，累加和无结模式n型和p型体硅FinFET的性能
4. Electrical performance of dense and isolated n-type FinFETs in micro-loading effect [C] . Mu-Chun Wang, Jian-Liang Lin, De-Huang Jhuang, International Symposium on Next-Generation Electronics . 2015

机译：微量负荷效应中致密和隔离N型FinFet的电气性能
5. Simulation of FinFET Electrical Performance Dependence on Fin Shape and TSV and Back-Gate Noise Coupling in 3-D Integrated Circuits. [D] . Gaynor, Brad. 2014

机译：取决于Fin形状和TSV以及3D集成电路中背栅噪声耦合的FinFET电性能仿真。
6. Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants [O] . Wen-Tsung Huang, Yiming Li 2015

机译：随机离散掺杂剂引起的具有固定顶鳍宽度的16nm栅极梯形体FinFET器件的电特性波动
7. The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances [O] . Jeong-kyu Kim, Gwang-sik Kim, Hyohyun Nam, 2016

机译：金属 - 界面层 - 半导体源/漏结构对亚10nm n型Ge FinFET性能的影响
8. Breakthroughs in Analog and RF Circuit Performance through Steep Slope FinFETs. [R] . Gaillardon, P., Walker, R., Rodriguez, B. S. 2016

机译：通过陡峭斜率FinFET实现模拟和RF电路性能的突破。

Electrical performance of dense and isolated n-type FinFETs in micro-loading effect

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