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An efficient layered ABV methodology for vision system on chip based on heterogeneous parallel processors

机译：基于异构并行处理器的片上视觉系统的高效分层ABV方法

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The demand of higher performance system on chip (SoC) based on massively parallel processors has increased significantly throughout the last decades. The design verification of the chip becomes one of the major challenges in microelectronics. The paper proposes an efficient Layered Assertion Based Verification (L-ABV) methodology for vision system on chip based on heterogeneous parallel processors. It focuses on the vision SoC pre-silicon verification solutions. First, we discuss on how to reduce the degree of dependency between verification task and design task. Then we split the verification task into different logic layers. L-ABV has been successfully used in Vision SoC to increase the verification productivity. The result shows that it has effectively shortened the verification time.
机译：在过去的几十年中，基于大规模并行处理器的高性能片上系统（SoC）的需求已大大增加。芯片的设计验证成为微电子学的主要挑战之一。本文提出了一种基于异构并行处理器的片上视觉系统的高效分层断言基于验证（L-ABV）的方法。它专注于视觉SoC预硅验证解决方案。首先，我们讨论如何减少验证任务和设计任务之间的依赖程度。然后，我们将验证任务分为不同的逻辑层。 L-ABV已成功用于Vision SoC中，以提高验证效率。结果表明，它有效地缩短了验证时间。

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