Low voltage adaptive delay clock buffer design

机译：低压自适应延迟时钟缓冲器设计

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Power consumption becomes issue in circuit design, and low voltage design is a good candidate for low power. However, the timing variation becomes greater when supply voltage scales down to near-threshold resign. The existing methods could not work well at low voltage. We propose a new clock buffer which can get low variation at near-threshold. Our proposal reduces the variation from 139% to 30.3% of 7 level buffer compared to normal buffer, at 0.4V, 32/28nm technology.

机译：功耗成为电路设计中的问题，低压设计是低功耗的理想选择。但是，当电源电压按比例缩小至接近阈值时，时序变化会变得更大。现有方法在低压下不能很好地工作。我们提出了一个新的时钟缓冲器，该缓冲器可以在接近阈值时获得较小的变化。我们建议在0.4V，32 / 28nm技术下，将7级缓冲器的变化从139％降低到30.3％，与普通缓冲器相比。

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《IEEE International Conference on ASIC》|2015年|1-4|共4页
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Yafei Liu; Xiangyu Li;
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Delays; Clocks; Low voltage; Transistors; Threshold voltage; Voltage control; Inverters;

机译：延迟;时钟;低电压;晶体管;阈值电压;电压控制;逆变器;

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1. 新的被动自适应起落架缓冲器设计与着陆性能研究 [J] . 朱书华, 童明波, 许杰南京航空航天大学学报（英文版） . 2009,第001期
2. Load-Balanced Clock Tree Synthesis with Adjustable Delay Buffer Insertion for Clock Skew Reduction in Multiple Dynamic Supply Voltage Designs [J] . KUAN-YU LIN, HONG-TING LIN, TSUNG-YI HO, ACM Transactions on Design Automation of Electronic Systems . 2012,第3期

机译：负载平衡时钟树综合与可调延迟缓冲器插入，可减少多种动态电源电压设计中的时钟偏斜
3. Esteem Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multiple Dynamic Supply Voltage Design [J] . Erugurala Supriya, Sridevi Reddy Advances in computational sciences and technology . 2017,第10期

机译：可调延迟缓冲器的Esteem分配，用于在多个动态电源电压设计中最小化时钟偏斜
4. Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers [J] . Su Y.-S., Hon W.-K., Yang C.-C., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2010,第12期

机译：使用可调延迟缓冲器的多电压模式设计中的时钟偏移最小化
5. Low voltage adaptive delay clock buffer design [C] . Yafei Liu, Xiangyu Li IEEE International Conference on ASIC . 2015

机译：低压自适应延迟时钟缓冲器设计
6. Design, Implementation and Experimental Verification of Low Voltage Buffers, Miller Op-amps, Ldo, and Fully-integrated All-pass Filters with Very High Figures of Merit [D] . Paul, Anindita . 2019

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7. High Breakdown Voltage and Low Buffer Trapping in Superlattice GaN-on-Silicon Heterostructures for High Voltage Applications [O] . Alaleh Tajalli, Matteo Meneghini, Sven Besendörfer, 2020

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Low voltage adaptive delay clock buffer design

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