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Low Power 3-Bit Flash ADC Design with Leakage Power Reduction at 45 nm Technology

机译：低功耗3位闪光ADC设计，具有45 nm技术的漏功率降低

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摘要

Most of the signals encountered in real world are analog in nature. Analog-to-digital converters are needed for conversion of an analog signal into digital signal. These converters can be implemented by using different available architectures. The performance of a converter is mainly analyzed based on its speed, area and power. Selection of a particular architecture totally depends upon its application. In this paper, the focus is on dynamic power, static power and delay of an ADC. Threshold Modified Comparator Circuit (TMCC) is used to reduce power dissipation. The work includes use of Self Controllable Voltage Level (SVL) technique to design a flash ADC for reduction of the leakage power. The simulation results of such ADC have been compared at 180 nm and at 45 nm technology. The proposed ADC has 41.12 μW dynamic power dissipation at 10 MHz frequency and 2.12 n W static power dissipation for 1.8 V at 45nm technology node. This data gets reduced to 1.866 μW dynamic power dissipation at the same frequency and static power gets reduced to 119.3 pW for 1.1V at 45nm. The software used for the designing and analysis purpose is Cadence Virtuoso version IC6.1.5.500.14.
机译：现实世界中遇到的大多数信号都是模拟的。需要模拟到数字转换器以将模拟信号转换为数字信号。这些转换器可以通过使用不同的可用体系结构来实现。转换器的性能主要根据其速度，区域和功率进行分析。特定架构的选择完全取决于其应用。在本文中，重点是动态功率，静态功率和ADC的延迟。阈值改性比较器电路（TMCC）用于降低功耗。该工作包括使用自控电压电平（SVL）技术来设计闪光ADC，以降低泄漏功率。这种ADC的仿真结果已在180nm和45nm的技术下进行了比较。所提出的ADC具有41.12μW动态功耗，10 MHz频率，45nm技术节点为1.8 V静态功耗。此数据降低至1.866μW动态功耗，在相同的频率下，静电功率降至45nm的119.3 PW 1.1V。用于设计和分析目的的软件是Cadence Virtuoso版IC6.1.5.500.14。

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