Carbon nanotube enhanced CMOS interconnect

机译：碳纳米管增强型CMOS互连

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This paper describes the potential of using carbon nanotube (CNT) as a via-filling material to enhance the performance mainstream CMOS technology. Due to the CMOS compatibility constraint, the choice of catalyst material and processing conditions have been significantly limited. After a careful selection process, Ni is found to be a workable material. Through catalyst engineering, we have demonstrated that it is possible to form CNT filled vias on metal or silicide substrate at low temperature with low contact resistance. The impact of via dimensions and processing condition has also been studied. Based on statistical analysis using measured data, the best-case projected via resistance for a 30nm via is 295Ω, which is within one order of magnitude of its copper and tungsten counterparts.

机译：本文介绍了使用碳纳米管（CNT）作为通孔填充材料来增强主流CMOS技术性能的潜力。由于CMOS兼容性的限制，催化剂材料和工艺条件的选择受到了很大的限制。经过仔细的选择过程，发现镍是一种可行的材料。通过催化剂工程，我们已经证明可以在低温下以低接触电阻在金属或硅化物衬底上形成CNT填充通孔。还研究了通孔尺寸和加工条件的影响。根据使用测量数据的统计分析，对于30nm通孔，最佳情况下的通孔电阻预测值为295Ω，这是其铜和钨对应物的一个数量级。

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《IEEE International Nanoelectronics Conference》|2016年|1-3|共3页
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Suwen Li; Changjian Zhou; Salahuddin Raju; Mansun Chan;
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Nickel; Electrodes; Carbon nanotubes; Silicides; Resistance; CMOS technology;

机译：镍;电极;碳纳米管;硅化物;电阻; CMOS技术;

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专利

1. Carbon Nanotube Contact Plug on Silicide for CMOS Compatible Interconnect [J] . Suwen Li, Salahuddin Raju, Changjian Zhou, IEEE Electron Device Letters . 2016,第6期

机译：用于CMOS兼容互连的硅化物上的碳纳米管接触塞
2. Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics [J] . Chen X., Akinwande D., Lee K.-J., Electron Devices, IEEE Transactions on . 2010,第11期

机译：用于千兆赫兹高速CMOS电子产品的完全集成石墨烯和碳纳米管互连
3. Measurement of Subnanosecond Delay Through Multiwall Carbon-Nanotube Local Interconnects in a CMOS Integrated Circuit [J] . Close G. F., Yasuda S., Paul B. C., IEEE Transactions on Electron Devices . 2009,第1期

机译：通过CMOS集成电路中的多壁碳纳米管局部互连来测量亚纳秒延迟
4. Applications of carbon-nanotubes in CMOS interconnect technology enhancement [C] . Salahuddin Raju, Changjian Zhou, Suwen Li, IEEE International Conference on Solid-State and Integrated Circuit Technology . 2016

机译：碳纳米管在CMOS互连技术增强中的应用
5. High-frequency impedance extraction of interconnects considering substrate effects and exploration of single-walled carbon nanotubes for future VLSI interconnects. [D] . Srivastava, Navin. 2009

机译：考虑衬底效应的互连线的高频阻抗提取和用于未来VLSI互连线的单壁碳纳米管的探索。
6. Synthesis of Vertical Carbon Nanotube Interconnect Structures Using CMOS-Compatible Catalysts [O] . Zichao Ma, Shaolin Zhou, Changjian Zhou, 2020

机译：CMOS相容催化剂的垂直碳纳米管互连结构的合成
7. Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics [O] . Xiangyu Chen, Deji Akinwande, Kyeong-Jae Lee, 2010

机译：用于Gigahertz高速CMOS电子的完全集成的石墨烯和碳纳米管互连

Carbon nanotube enhanced CMOS interconnect

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