• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>International Conference on Sciences and Techniques of Automatic Control and Computer Engineering >Hardware complexity reduction of LDPC-CC decoders based on message-passing approaches
【24h】

Hardware complexity reduction of LDPC-CC decoders based on message-passing approaches

机译：基于消息传递方法的LDPC-CC解码器的硬件复杂度降低

获取原文
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

LDPC convolutional codes (LDPC-CC) are a family of error-correcting codes (ECC) used in digital communication systems like the IEEE 1901 standard. High throughput and low complexity hardware architectures were designed for real time systems. In this article we demonstrate that an efficient selection of the message passing (MP) algorithm for LDPC-CC decoding improves the architecture features of related works. In fact, considering the LDPC-CC decoders proposed for the IEEE 1901 standard, we show that an appropriate Min-Sum approximation selection can significantly improve the error correction performance by 0.1 to 0.2 dB in terms of Bit Error Ratio. It can also reduce the hardware complexity by 10% to 20% with no impact on the Bit Error Ratio performance.
机译：LDPC卷积码（LDPC-CC）是在像IEEE 1901标准这样的数字通信系统中使用的纠错码（ECC）系列。高吞吐量和低复杂度的硬件体系结构是为实时系统设计的。在本文中，我们证明了有效选择LDPC-CC解码的消息传递（MP）算法可以改善相关工作的体系结构。实际上，考虑到针对IEEE 1901标准提出的LDPC-CC解码器，我们表明适当的Min-Sum近似选择可以在误码率方面将纠错性能显着提高0.1至0.2 dB。它还可以将硬件复杂度降低10％至20％，而不会影响误码率性能。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号