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首页> 外文会议>International workshop on cryptographic hardware and embedded systems >A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation
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A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation

机译：通过压缩加密和解密数据路径的高吞吐量/门AES硬件架构-迈向高效的CBC模式实施

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This paper proposes a highly efficient AES hardware architecture that supports both encryption and decryption for the CBC mode. Some conventional AES architectures employ pipelining techniques to enhance the throughput and efficiency. However, such pipelined architectures are frequently unfit because many practical cryptographic applications work in the CBC mode, where block-wise parallelism is not available for encryption. In this paper, we present an efficient AES encryption/decryption hardware design suitable for such block-chaining modes. In particular, new operation-reordering and register-retiming techniques allow us to unify the inversion circuits for encryption and decryption (i.e., SubBytes and InvSubBytes) without any delay overhead. A new unification technique for linear mappings further reduces both the area and critical delay in total. Our design employs a common loop architecture and can therefore efficiently perform even in the CBC mode. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption architectures with tower-field S-boxes. We evaluate the performance of the proposed and some conventional datapaths by logic synthesis results with the TSMC 65-nm standard-cell library and Nan-Gate 45- and 15-nm open-cell libraries. As a result, we confirm that our proposed architecture achieves approximately 53-72% higher efficiency (i.e., a higher bps/GE) than any other conventional counterpart.
机译：本文提出了一种高效的AES硬件体系结构，该体系结构支持CBC模式的加密和解密。一些传统的AES体系结构采用流水线技术来提高吞吐量和效率。但是，这种流水线体系结构经常不合适，因为许多实际的密码应用程序都在CBC模式下工作，在这种模式下，分块并行性不可用于加密。在本文中，我们提出了适用于此类块链接模式的有效AES加密/解密硬件设计。特别地，新的操作重排序和寄存器重定时技术使我们能够统一用于加密和解密的反转电路（即，SubByte和InvSubByte），而没有任何延迟开销。线性映射的新统一技术进一步减少了面积和总体上的临界延迟。我们的设计采用了通用的循环架构，因此即使在CBC模式下也可以有效执行。我们还提出了一个共享密钥调度数据路径，该路径可以在建议的体系结构中即时运行。据我们所知，在具有塔场S盒的传统AES加密/解密体系结构中，所提出的体系结构具有最短的关键路径延迟，并且在每单位面积的吞吐量方面是最有效的。我们通过台积电65纳米标准单元库和Nan-Gate 45纳米和15纳米开放单元库的逻辑综合结果，评估了建议的和某些常规数据路径的性能。结果，我们确认，我们提出的架构比其他任何常规同类产品都可获得大约53-72％的效率提高（即更高的bps / GE）。

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