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On the Dark Silicon Automatic Evaluation on Multicore Processors

机译：关于多核处理器的暗硅自动评估

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The advent of Dark Silicon as result of the limit on Dennard scaling forced modern processor designs to reduce the chip area that can work on maximum clock frequency. This effect reduced the free gains from Moore's law. This work introduces a less conservative dark silicon estimate based on chip components power density and technological process, so that designers could explore architectural resources to mitigate it. We implemented our dark silicon estimation tool on top of MultiExplorer and evaluated on a set of Intel Pentium and AMD K8/10 multicore processors built on transistor technologies from 90nm down to 32nm. Our contributions are twofold: (1) Our experiments have shown dark silicon estimates up to 8.26% of the chip area compared to a baseline 90nm real processor, we also evaluated clock frequency behavior based on Dennard scaling and obtained up to 15.65% dark silicon on chip area. (2) We designed and showed that a dark silicon aware Design Space Exploration (DSE) strategy can minimize chip dark area while increasing performance at design time. Our results on DSE found dark silicon free multicore platforms while providing 3.6 speedup.
机译：由于Dennard缩放限制的出现，Dark Silicon的出现迫使现代处理器设计减小了可以在最大时钟频率下工作的芯片面积。这种影响减少了摩尔定律的自由收益。这项工作引入了一种基于芯片组件功率密度和工艺流程的保守度较低的深色硅估算，以便设计人员可以探索架构资源来减轻这种负担。我们在MultiExplorer之上实现了暗硅评估工具，并基于基于90nm至32nm晶体管技术的一组Intel Pentium和AMD K8 / 10多核处理器进行了评估。我们的贡献是双重的：（1）我们的实验表明，与基准90nm真实处理器相比，暗硅估计占芯片面积的8.26％，我们还根据Dennard缩放比例评估了时钟频率行为，并获得了多达15.65％的暗硅。芯片面积。 （2）我们设计并表明，了解暗硅的设计空间探索（DSE）策略可以最大程度地减少芯片暗区，同时提高设计时的性能。我们在DSE上的结果发现了无硅的多核平台，同时提供了3.6的加速。

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