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首页> 外文会议>International Symposium on Computer Architecture and High Performance Computing Workshop >Dataflow to Hardware Synthesis Framework on FPGAs
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Dataflow to Hardware Synthesis Framework on FPGAs

机译：FPGA上的硬件综合框架的数据流

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We present a dataflow based performance estimation and synthesis framework that will help hardware designers quantify the algorithm performance and synthesize their HW designs onto Field Programmable Gate Arrays (FPGAs). Typically, Digital Signal Processing (DSP) systems are designed by making gradual architectural choices in HW refinement steps. These decisions are based on performance quantification by high level DSP algorithm developers and HW implementation engineers. The main obstacle to this refinement is the provision of reasonably correct performance estimations to guide HW designers in Design Space Exploration (DSE) at an early stage. HW designers face challenges when they need to quantify the performance of their designs, especially when resources are limited. We use dataflow models by describing their hardware detail only as necessary. Dataflow based performance estimation achieves the efficient generation of qualitative and quantitative parameters for the assessment of HW candidates. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, FPGAs can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration from the dataflow to synthesized HDL design. Experimental results show a linear speedup by adding reasonably small processing elements in FPGA as opposed to using a software implementation running on a typical general purpose processor.
机译：我们提出了一个基于数据流的性能估计和综合框架，该框架将帮助硬件设计人员量化算法性能并将其硬件设计综合到现场可编程门阵列（FPGA）上。通常，通过在硬件优化步骤中逐步选择架构来设计数字信号处理（DSP）系统。这些决定基于高级DSP算法开发人员和硬件实现工程师的性能量化。这种改进的主要障碍是提供合理正确的性能估算，以在早期阶段指导HW设计人员进行设计空间探索（DSE）。硬件设计师在需要量化设计性能时面临挑战，尤其是在资源有限的情况下。我们仅通过在必要时描述数据流模型的硬件细节来使用数据流模型。基于数据流的绩效评估可有效生成定性和定量参数，以评估硬件候选人。与在通用处理器上执行内核相比，可重新配置逻辑可用于将主计算内核卸载到自定义计算机上，从而将执行时间减少一个数量级。具体而言，FPGA可以用于使用基于硬件的自定义逻辑实现来加速这些内核。在本文中，我们演示了从数据流到综合HDL设计的算法加速框架。实验结果表明，与在典型的通用处理器上运行的软件实现相反，通过在FPGA中添加相当小的处理元素可以实现线性加速。

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