0.5V 1OMS/S 9-Bits Asynchronous SAR ADC for BLE Receivers in L80NM CMOS Technology

机译：0.5V 1OMS / S 9位异步SAR ADC用于L80NM CMOS技术的BLE接收器

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This work presents the design and measured results of a 9-bit 10MS/s asynchronous SAR ADC at 0.5V of supply voltage for Bluetooth Low Energy RF receivers. The ADC was designed in 180nm CMOS technology using low-Vt transistors in order to operate in ultra-low supply voltage. A dynamic comparator and a bootstrapped circuit topologies, adequate for low voltage SAR ADCs with low power operation and moderate speed are proposed in this work. The experimental power consumption of the fabricated circuit is 48μW at 10MS/s, with 8.55-bit of ENOB and FoM of 13fJ/step.

机译：这项工作介绍了9位10ms / s异步SAR ADC的设计和测量结果，适用于蓝牙低能量RF接收器的电源电压0.5V。 ADC设计在180nm CMOS技术中，使用低VT晶体管，以便以超低电源电压运行。在这项工作中提出了一种动态比较器和引导的电路拓扑，适用于低电压SAR ADC，在这项工作中提出了低功耗和中等速度。制造电路的实验功率消耗为48μW，10ms / s，18.55位ENOB和13FJ /步骤的FOM。

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来源
《IEEE International System-on-Chip Conference》|2018年|329p|共4页
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作者
Hugo Hernandez; Lucas Severo; Wilhelmus Van Noije;
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原文格式 PDF
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中图分类 TN40-53;
关键词
Transistors; Latches; Clocks; Capacitors; Power demand; Logic gates; CMOS technology;

机译：晶体管;闩锁;时钟;电容;电源;逻辑门;CMOS技术;

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1. 14.5 fJ/conversion-step 9-bit 100-kS/s non-binary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS [J] . Jagadish Dasarahalli Narasimaiah, Mujoor Shankaranarayana Bhat Circuits, Devices & Systems, IET . 2018,第6期

机译：14.5 fJ /转换步长为90 nm CMOS的9位100-kS / s非二进制加权双电容阵列面积和节能SAR ADC
2. A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS [J] . Palani Rakesh Kumar, Harjani Ramesh Circuits and Systems II: Express Briefs, IEEE Transactions on . 2015,第11期

机译：在65nm CMOS中具有133fF输入电容和37fJ / conv FOM的220-MS / s 9位2X时间交错SAR ADC
3. A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors [J] . Chen D.G., Tang F., Law M.-K., Circuits and Systems I: Regular Papers, IEEE Transactions on . 2014,第11期

机译：具有前向纠错功能和混合信号CDS的64 fJ / step 9位SAR ADC阵列，用于CMOS图像传感器
4. 0.5V 1OMS/S 9-Bits Asynchronous SAR ADC for BLE Receivers in L80NM CMOS Technology [C] . Hugo Hernandez, Lucas Severo, Wilhelmus Van Noije IEEE International System-on-Chip Conference . 2018

机译：适用于L80NM CMOS技术的BLE接收器的0.5V 1OMS / S 9位异步SAR ADC
5. High-Speed SAR ADC Design in SIGE BiCMOS Technology [D] . Hermansen, Peter. 2019

机译：采用SIGE BiCMOS技术的高速SAR ADC设计
6. A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs [O] . Min-Kyu Kim, Seong-Kwan Hong, Oh-Kyong Kwon 2016

机译：具有列并行12位SAR ADC的低噪声CMOS图像传感器的快速多重采样方法
7. A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS [O] . Manxin Li, Yuting Yao, Biao Hu, 2021

机译：6.94-FJ /转换 - 步骤12位100-MS / S异步SAR ADC在65-NM CMOS中利用分割CDAC

0.5V 1OMS/S 9-Bits Asynchronous SAR ADC for BLE Receivers in L80NM CMOS Technology

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