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A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs

机译：本密码的高性能VLSI架构及其对SOC的实现

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摘要

The essence of internet-of-things (IoT) and cyber-physical systems (CPS) infrastructures is primarily based on privacy and security of communicated data. In these resource-constrained applications, lightweight cryptography plays a vital role for data security. In this paper, we propose a high-performance and power-efficient VLSI architecture for the PRESENT block cipher and its integration in a system-on-chip (SoC) environment. The architecture is based on 8-bit datapath and requires 48 clock cycles for processing of 64-bit plaintext and 128-bit key. When implemented on Xilinx Virtex-5 xc5vlx50-1ff324 FPGA device, it consumes 84 slices, provides 379.78 MHz maximum frequency, and 506.37 Mbps of throughput. Dynamic power consumption is 36.57 mW, energy 57.95 nJ, and energy/bit is 0.91 nJ/bit. In comparison to an exiting architecture, the proposed architecture provides improved performance. Further, an ASIC implementation of the architecture is done in SCL 180 nm technology for its usage as an intellectual-property (IP) core for SoCs. Gate count of the ASIC implementation is 1785 GE, area 1.55 mm2, and it can be operated up to 448 MHz clock frequency.
机译：互联网上的本质（物联网）和网络物理系统（CPS）基础架构主要基于传送数据的隐私和安全性。在这些资源约束应用程序中，轻量级密码术对数据安全起作用至关重要的作用。在本文中，我们为当前块密码提出了高性能和高效的VLSI架构及其在片上系统（SOC）环境中的集成。该体系结构基于8位数据路径，需要48个时钟周期，以处理64位明文和128位键。在Xilinx Virtex-5 XC5VLX50-1FF324 FPGA设备上实现时，它会消耗84个切片，提供379.78 MHz的最大频率和506.37 Mbps的吞吐量。动态功耗为36.57 MW，Energy 57.95 NJ和能量/位为0.91 NJ /位。与退出架构相比，所提出的架构提供了改进的性能。此外，架构的ASIC实现是在SCL 180nm技术中完成的，以便其用作SOC的知识产权（IP）核心。 ASIC实现的栅极计数为1785 GE，面积1.55毫米 2 ，它可以操作高达448 MHz时钟频率。

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