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Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs

机译：用于下一代FPGA的优化基于计数的多端口内存架构

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摘要

With the dramatic increase in utilization of FPGAs to accelerate compute/data intensive applications on embedded platforms, providing customized/optimized multi-ported memory architectures for FPGAs are of paramount importance. FPGAs achieve high speedup by exploiting parallelism in computations, which requires multi-ported memories to provide any number of ports for simultaneous and multiple read/write (R/W) operations. Most of the existing multi-ported memory designs become complex due to the extra logic and routing required to provide an arbitrary number of R/W ports. In this paper, we introduce four unique, novel, and optimized counter-based multi-ported memory architectures. With our memories, circular paths are eliminated; thus significantly reducing the design/routing complexity, while enhancing the operating frequency and area-efficiency. As a result, our memories can be seamlessly integrated to the existing and next-generation FPGAs. Our proposed memories are evaluated with the most recent multi-ported memory designs in the literature.
机译：随着FPGA利用率的显着增加，可以加速嵌入式平台上的计算/数据密集型应用，为FPGA提供定制/优化的多端口内存架构是至关重要的。 FPGA通过在计算中利用并行性来实现高速度，这需要多端口存储器来提供任何数量的端口，用于同时和多读/写（R / W）操作。由于提供任意数量的R / W端口所需的额外逻辑和路由，大多数现有的多端口存储器设计变得复杂。在本文中，我们介绍了四种独特的新颖，优化的基于基于对的多端口内存架构。通过我们的回忆，消除了圆形路径;从而显着降低了设计/路由复杂性，同时提高了运行频率和面积效率。因此，我们的存储器可以无缝地集成到现有和下一代FPGA。我们所提出的记忆在文献中的最新多移植内存设计中评估。

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