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Design of a power-efficient ARM processor with a timing-error detection and correction mechanism

机译:具有定时错误检测和校正机制的功率高效臂处理器的设计

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With the growing popularity of mobile devices, the trend in the field of system-on-chip has shifted from high performance to low power operation. However, traditional design methodology is limited by the design margins reserved for process, voltage and temperature variations. Therefore, a systematic solution that enables real-time timing error detection and correction was proposed to eliminate redundant margins in the design of an ARM microprocessor. A prototype stochastic ARM1136 processor was implemented in TSMC 90nm technology. Two circuit-level techniques, Razor and Surger, are exploited to form a hybrid error detection mechanism by observing both global and local timing information. To enable the deployment of aggressive voltage scaling with hardware-based error tolerance mechanism, we propose an activity-driven optimization flow to reshape the slack distribution based on path-activation probability. The chip achieves a frequency of 250MHz at worst case with 48.82mW power consumption. The overall power overhead of the proposed error tolerance mechanism is about 25% (hold-fixing latches 15.25% plus Razor 10.53%). The energy saving through design margins elimination is 51% (an average of the three corner cases) and a 42.8% saving was measured at the lowest operation voltage.
机译:随着移动设备的日益普及,片上系统领域的趋势已经从高性能转移到低功率操作。然而,传统的设计方法受到用于工艺,电压和温度变化的设计边距的限制。因此,提出了一种实现实时定时误差检测和校正的系统解决方案,以消除臂微处理器设计中的冗余边缘。在TSMC 90nm技术中实现了原型随机ARM1136处理器。通过观察全局和本地时序信息,利用两个电路级技术,剃刀和更突变者来形成混合误差检测机制。为了使得能够使用基于硬件的耐用电阻机制进行攻击性电压缩放,我们提出了一种活动驱动的优化流程,基于路径激活概率重塑松弛分布。该芯片在最坏情况下实现250MHz的频率,功耗为48.82MW。所提出的误差容差机制的总电源开销约为25%(固定闩锁15.25%加上剃须刀10.53%)。通过设计边距消除的节能为51%(三个角壳的平均值),在最低操作电压下测量42.8%的节省。

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