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首页> 外文会议>IEEE International System-on-Chip Conference >Automated Full Chip SPICE simulations with self-checking assertions for last mile verification first pass Silicon of mixed signal SoCs
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Automated Full Chip SPICE simulations with self-checking assertions for last mile verification first pass Silicon of mixed signal SoCs

机译：自动芯片SPICE模拟，用于上一英里验证的自检断言和混合信号SOC的首次通行证

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System-on-Chips designed for modern applications combine a large number of highly integrated Analog, Digital and Mixed-signal circuits. As we approach smaller technology nodes, semiconductor mask costs rise higher and higher. Thus the need to achieve first pass Silicon is even higher, so as to keep non-recurring engineering cost at a minimum, and eliminate Silicon debug time and mask re-spin costs. Moreover, the SOCs may be used for applications where safety and reliability are essential, requiring the SOC to be defect free. This can be achieved only if the SOC is designed and verified thoroughly, and is known to meet all design specifications. This is performed through verification at different levels: IP and SOC level; and different modes: RTL, SPICE and mixed-mode simulations. Yet chip wide electrical coverage still may have gaps. We present a flow that uses Full Chip SPICE simulations to plug this gap. By automating the FCS setup creation and making the results self-checking, we are able to increase coverage and uncover hidden defects not caught by any other method. We also provide Silicon results that correlate to findings made through FCS simulations.
机译：为现代应用设计的系统芯片组合了大量高度集成的模拟，数字和混合信号电路。当我们接近较小的技术节点时，半导体掩模成本更高且更高。因此，需要实现第一通道硅的需要甚至更高，以便保持非经常性的工程成本，并消除硅调试时间和掩模重新旋转成本。此外，SOC可以用于安全性和可靠性必不可少的应用，要求SOC自由缺陷。只有在彻底设计和验证SOC时，才能实现这一点，并且已知符合所有设计规范。这是通过不同级别的验证进行的：IP和SoC级别进行;和不同的模式：RTL，Spice和混合模式模拟。然而，芯片宽的电覆盖仍可能具有间隙。我们介绍了一种使用全芯片Spice模拟来插入这种间隙的流程。通过自动化FCS设置创建并使结果自检，我们能够增加任何其他方法未捕获的覆盖范围和揭示隐藏缺陷。我们还提供与通过FCS仿真制作的结果相关的硅结果。

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