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首页> 外文会议>IEEE International System-on-Chip Conference >Single-ended D flip-flop with implicit scan mux for high performance mobile AP
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Single-ended D flip-flop with implicit scan mux for high performance mobile AP

机译：具有隐式扫描MUX的单端D触发器，适用于高性能移动AP

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A novel high-speed single-ended D flip-flop based on a SR(set/reset)-type latch is presented in this paper. The SR-type latch is adapted to implement a dynamic stage for high-speed operation and modified to add a scan mux without setup time degradation on a data path. The proposed flip-flop enables to achieve the high-speed operation having the comparable hold time characteristics to a conventional master-slave flip-flop without any writeability issue at low voltage. The simulated and the measured results were made using a 14nm FinFET process. The data-to-output latency of the proposed flip-flop decreased by 51% while the power delay product improved by 41% as compared with the master-slave flip-flop. A test chip was fabricated in SS, TT, FF, SF and FS process corners and tested at -25C and 100C with a 50mV voltage step from 0.45V to 1.00V. It indicates both the master-slave and the proposed flip-flops can work down to 0.50V whereas conventional pulse-based flip-flops have writeability problems at 0.60V. Two product-level CPU designs were also fabricated for performance comparison, leading to 8.5% speed improvement by applying the proposed high-speed flip-flop.
机译：本文提出了一种基于SR（SET / RESET）-TYPE锁存器的新型高速单端D触发器。 SR型锁存器适于实现用于高速操作的动态级，并修改以添加扫描MUX而无需在数据路径上进行设置时间劣化。所提出的触发器使得能够实现具有与传统主从触发器的可比保持时间特性的高速操作，而没有任何在低电压下的备注问题。使用14nm FinFET过程进行模拟和测量结果。与主从触发器相比，所提出的触发器的数据 - 输出延迟减少了51％，而功率延迟产品随着主从触发器的增加而提高了41％。在SS，TT，FF，SF和FS工艺角落中制造测试芯片，并在-25℃和100℃下测试，50mV电压步长度为0.45V至1.00V。它表明主从和所提出的触发器都可以下降到0.50V，而常规的脉冲触发器具有0.60V的可卷合作用问题。还制造了两种产品级CPU设计以进行性能比较，通过应用所提出的高速触发器的速度提高8.5％。

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