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Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework

机译：异构内存装配探索使用平面图和互连感知框架

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Embedded SRAM based memory sub-systems are an integral part of SoCs and have a large area footprint in modern SoCs today. Huge memory requirements are typically met by using an array of SRAM instances and optimal selection of these memory instances becomes imperative for SoC designers. We propose a framework based on the following approach: pre-sort a list of most suitable SRAM instances; create a memory assembly using one of these SRAM instances; calculate total assembly area, power and performance of the resultant sub-system using estimation models; iterate through this process to find out the optimal memory assembly possible that conforms to the user-defined PPA criteria. This automated framework assists SoC designers to select an optimal SRAM instance from the potentially large number of combinations possible through generic memory compilers. Through this paper, we also demonstrate that the optimal memory solution can actually lie in using a combination of distinct memory instances, their characteristics varying on the type of optimization desired. We refer to this approach as approach of heterogeneous memory assemblies. These heterogeneous memory assemblies can potentially achieve even better performance than what can be achieved by homogeneity, whatever be the scope of optimization, viz. area, dynamic power or leakage optimization. Through our advanced memory sub-system exploration framework (MSSEF), we demonstrate that for a 4 M-bit memory requirement, we can achieve area savings up to 11 % by using a combination of heterogeneous memory instances instead of homogeneous assemblies.
机译：嵌入式SRAM基于内存子系统的系统级芯片的一个组成部分，在现代的SoC今天大面积的足迹。巨大的内存需求通常通过使用SRAM实例和这些存储器实例的最佳选择变得必要对SoC设计的阵列满足。我们建议基于以下方式的框架：预先排序最适合SRAM实例的列表;创建使用这些SRAM实例中的一个组件的存储器;计算总装配面积，功率，并使用估算模型所得的副系统的性能;迭代通过这个过程组件可能找出最佳内存符合用户定义的PPA的标准。这种自动化框架有助于SoC设计以从潜在的大量通过通用存储器编译器可能组合选择最佳的SRAM实例。通过本文中，我们还证明，最优存储器溶液实际上可以位于不同的使用存储器实例的组合，它们的特性最优化的类型变化的需要的话。我们称这种方法为异构存储组件的方法。这些异构存储组件有可能实现比可通过同质化来实现，无论是优化的范围，即更好的性能。面积，动态功耗或泄漏优化。通过我们先进的内存子系统探索框架（MSSEF），我们证明了一个4兆比特存储器的要求，我们可以通过异构存储的实例，而不是同质组件的组合实现面积节省高达11％。

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