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Design and ASIC acceleration of cortical algorithm for text recognition

机译：文本识别皮质算法的设计与ASIC加速度

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Cortical algorithms, inspired by the neocortex, promise to outperform conventional algorithms in unsupervised learning tasks, i.e. with unlabeled data. The aim of the work reported in this paper was to design and implement an application specific integrated circuit (ASIC) having a massive speedup of a cortical algorithm, as compared with a CPU baseline. This ASIC is designed to implement a scaled-down version of Sparsey, an algorithm based on structural and functional properties of the brain's cortex. The design was benchmarked on the Short Message Service (SMS) spam collection dataset from the UCI machine learning repository. It was found that the synthesis area and power consumption of a single column (i.e., mac or PE) are 0.122 mm2 and 5.15 mW using 45 nm technology and 0.171 mm2 and 7.94 mW using 65 nm technology. The processing time for a single frame was 3.075 μs (learning) and 0.675 μs (recognition). The performance speedup in learning and recognition modes of ASIC implementation was 203× and 843× times that of software implementation on a CPU based platform.
机译：灵感来自Neocortex的皮质算法，承诺在无监督的学习任务中优于常规算法，即未标记数据。本文报告的工作目的是设计和实施具有CPU基线的皮质算法的大规模加速的应用特定集成电路（ASIC）。该ASIC旨在实现缩小版本的Sparsy，一种基于大脑皮层的结构和功能性质的算法。该设计在短消息服务（SMS）垃圾邮件集数据集中是从UCI机器学习存储库的短信服务（SMS）垃圾邮件集数据集。发现使用65nm技术的45nm技术和0.171mm 2和7.94 mw，单柱（即，Mac或PE）的合成区域和功耗为0.122mm2和5.15mW。单个帧的处理时间为3.075μs（学习）和0.675μs（识别）。 ASIC实现的学习和识别模式中的性能加速为CPU基于平台上的软件实现的203×和843倍。

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