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首页> 外文会议>Symposium on Mass Storage Systems and Technologies >REAL: A retention error aware LDPC decoding scheme to improve NAND flash read performance
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REAL: A retention error aware LDPC decoding scheme to improve NAND flash read performance

机译：REAL：具有保留错误意识的LDPC解码方案，可提高NAND闪存读取性能

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摘要

Continuous technology scaling makes NAND flash cells much denser. As a result, NAND flash is becoming more prone to various interference errors. Due to the hardware circuit design mechanisms of NAND flash, retention errors have been recognized as the most dominant errors, which affect the data reliability and flash lifetime. Furthermore, after experiencing a large number of programm/erase (P/E) cycles, flash memory would suffer a much higher error rate, rendering traditional ECC codes (typically BCH codes) insufficient to ensure data reliability. Therefore, low density parity check (LDPC) codes with stronger error correction capability are used in NAND flash-based storage devices. However, directly using LDPC codes with belief propagation (BP) decoding algorithm introduces non-trivial overhead of decoding latency and hence significantly degrades the read performance of NAND flash. It has been observed that flash retention errors show the so-called numerical-correlation characteristic (i.e., the 0-1 bits stored in the flash cell affect each other with the leakage of the charge) in each flash cell. In this paper, motivated by the observed characteristic, we propose REAL: a retention error aware LDPC decoding scheme to improve NAND flash read performance. The developed REAL scheme incorporates the numerical-correlation characteristic of retention errors into the process of LDPC decoding, and leverages the characteristic as additional bits decision information to improve its error correction capabilities and decrease the decoding latency. Our simulation results show that the proposed REAL scheme can reduce the LDPC decoding latency by 26.44% and 33.05%, compared with the Logarithm Domain Min-Sum (LD-MS) and Probability Domain BP (PD-BP) schemes, respectively.
机译：持续的技术扩展使NAND闪存单元更加密集。结果，NAND闪存变得更容易出现各种干扰错误。由于NAND闪存的硬件电路设计机制，保留错误已被认为是最主要的错误，这会影响数据可靠性和闪存寿命。此外，在经历大量的编程/擦除（P / E）周期后，闪存将遭受更高的错误率，从而使传统ECC代码（通常为BCH代码）不足以确保数据可靠性。因此，在基于NAND闪存的存储设备中使用具有更强的纠错能力的低密度奇偶校验（LDPC）码。但是，直接将LDPC码与信念传播（BP）解码算法一起使用会带来解码延迟的不小的开销，因此会大大降低NAND闪存的读取性能。已经观察到，在每个闪存单元中，闪存保持误差显示出所谓的数值相关特性（即，存储在闪存单元中的0-1位由于电荷的泄漏而彼此影响）。在本文中，基于观察到的特性，我们提出了REAL：一种具有保留错误意识的LDPC解码方案，以提高NAND闪存的读取性能。开发的REAL方案将保留错误的数字相关特性纳入LDPC解码过程，并利用该特性作为附加位决策信息来提高其纠错能力并减少解码等待时间。我们的仿真结果表明，与对数域最小和（LD-MS）和概率域BP（PD-BP）方案相比，所提出的REAL方案可以分别将LDPC解码延迟减少26.44％和33.05％。

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