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Automatic detection and elision of reset sub-circuits

机译：自动检测和清除复位子电路

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Electronic circuits are too complex to be designed by hand so hardware languages, like Verilog, and Computer Aided Design (CAD) tools are used for these purposes. Two main types of circuits are Application-Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs). ASICs require a reset sub-circuit to initialize their state; however, such a procedure is not necessary for FPGAs that support power-on reset. We propose and evaluate a tool that automatically detects and elides reset sub-circuits as part of the Verilog-to-Routing (VTR) CAD flow and in particular Odin II. Also, our tool can be used to decide if a reset sub-circuit has been properly implemented and can point towards memory components that have not been initialized. Such a tool is the first to our knowledge. Our tests with the VTR Verilog benchmarks and other Verilog circuits showed significant reductions in resource consumption on the target FPGAs as much as 25.9% shorter critical path, 90.39% shorter maximum net, 62.84% fewer used logic blocks and 30.87% fewer used routing elements. Also, our approach yielded significant reductions in the execution time of the placement-and-routing algorithm for the elided circuits that were as high as 4.5 times faster VPR execution and 3.35 times faster overall VTR flow execution.
机译：电子电路过于复杂，无法手工设计，因此硬件语言（例如Verilog）和计算机辅助设计（CAD）工具用于这些目的。两种主要类型的电路是专用集成电路（ASIC）和现场可编程门阵列（FPGA）。 ASIC需要一个复位子电路来初始化其状态。但是，对于支持上电复位的FPGA，这种过程不是必需的。我们提出并评估一种工具，该工具可以自动检测并消除重置子电路，这是Verilog到路由（VTR）CAD流程，尤其是Odin II的一部分。同样，我们的工具可用于确定是否正确实施了复位子电路，并且可以指向尚未初始化的存储器组件。这种工具是我们所知的第一个工具。我们在VTR Verilog基准测试和其他Verilog电路上进行的测试表明，目标FPGA上的资源消耗显着减少，关键路径缩短了25.9％，最大净网络缩短了90.39％，逻辑逻辑块减少了62.84％，路由元件减少了30.87％。同样，我们的方法大大减少了用于隐蔽电路的布局和路由算法的执行时间，该速度高达VPR执行速度的4.5倍和VTR流整体执行速度的3.35倍。

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