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首页> 外文会议>IEEE International Symposium on Rapid System Prototyping >HAMEX: heterogeneous architecture and memory exploration framework
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HAMEX: heterogeneous architecture and memory exploration framework

机译：HAMEX：异构体系结构和内存探索框架

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摘要

The increasing amount of computation in heterogeneous architectures (including CPU and GPU cores) puts a big burden on memory subsystem. With the gap between compute units and the memory performance getting wider, designing a platform with a responsive memory system becomes more challenging. This issue is exacerbated when memory systems have to satisfy a high volume of traffic generated from heterogeneous compute units. Furthermore, as emerging memory technologies are being introduced to address these issues, a rapid and flexible mechanism is needed to evaluate these technologies in the context of heterogeneous architectures. This paper proposes HAMEX, a framework that enables early design space exploration of heterogeneous systems with a focus on resolving memory access bottlenecks. This framework first allows system designers to easily model heterogeneous architectures that can run both CPU and GPU workloads. Next, given a set of workloads partitioned on various compute units, traffic generated by these units are captured in order to explore different memory systems. We show the feasibility of design space exploration using HAMEX by simulating a contemporary commercial heterogeneous platform and explore the opportunities for power and performance improvements by adopting different memory technologies.
机译：异构体系结构（包括CPU和GPU内核）中不断增加的计算量给内存子系统带来了沉重负担。随着计算单元之间的差距和内存性能的不断扩大，设计具有响应式内存系统的平台变得更具挑战性。当存储系统必须满足从异构计算单元生成的大量流量时，此问题会更加严重。此外，由于引入了新兴的存储器技术来解决这些问题，因此需要一种快速灵活的机制来在异构体系结构的背景下评估这些技术。本文提出了HAMEX，这是一个框架，可用于对异构系统进行早期设计空间探索，重点是解决内存访问瓶颈。该框架首先允许系统设计人员轻松地建模可同时运行CPU和GPU工作负载的异构体系结构。接下来，给定在不同计算单元上划分的一组工作负载，捕获由这些单元生成的流量，以探索不同的内存系统。我们通过模拟当代的商业异构平台，展示了使用HAMEX进行设计空间探索的可行性，并通过采用不同的存储技术探索了在功率和性能方面进行改进的机会。

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