Synthesis of a microelectronic structure of a specialized processor for sorting an array of binary numbers

机译：用于排序二进制数数组的专用处理器的微电子结构的综合

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Methods for graphical representation of algorithms of sorting arrays of binary numbers were analyzed. Improved schematic solution for structure development and components of specialized processor for sorting an array of binary numbers by “bubbles” method was represented. As a result, high-performance structures of specialized processors for sorting an array of binary numbers on FPGA were synthesized. System characteristics of hardware and time complexity of this class of processors targeted at microelectronic implementation in structure of embedded systems were calculated.

机译：分析了二进制数排序数组算法的图形表示方法。提出了一种改进的用于结构开发和专用处理器组件的示意性解决方案，该解决方案用于通过“气泡”方法对二进制数数组进行排序。结果，合成了用于在FPGA上对二进制数进行排序的专用处理器的高性能结构。计算了针对嵌入式系统结构中的微电子实现的此类处理器的系统硬件特性和时间复杂度。

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《International Conference on Perspective Technologies and Methods in MEMS Design》|2017年|170-173|共4页
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Volodymyr Gryga; Yaroslav Nykolaichuk; Nataliia Vozna; Boris Krulikovskyi;
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Sorting; Hardware; Field programmable gate arrays; Algorithm design and analysis; Complexity theory; Multiplexing; Logic gates;

机译：分类;硬件;现场可编程门阵列;算法设计与分析;复杂性理论;复用;逻辑门;

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8. Design, Processing and Testing of Lsi Arrays, Hybrid Microelectronics Task [R] . Himmel, R. P., Stuhlbarg, S. M., Ravetti, R. G., 1979

机译：Lsi阵列的设计，加工和测试，混合微电子任务

Synthesis of a microelectronic structure of a specialized processor for sorting an array of binary numbers

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