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首页> 外文会议>Conference on Ph.D. Research in Microelectronics and Electronics >Analysis of array biasing in crosspoint memories for leakage power minimization
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Analysis of array biasing in crosspoint memories for leakage power minimization

机译：分析交叉点存储器中的阵列偏置以最小化功耗

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Thanks to the recent development of resistance-switching memories, crosspoint array has become an attractive architecture to obtain high-density storage. However, crosspoint arrays suffer from sneak current paths and voltage drops on interconnection lines, which may lead to various challenges such as excessive leakage power, write failure, write disturbance, and insufficient read margin. In this paper we focus our attention on leakage power consumption. We demonstrate that the bias scheme that minimizes leakage power consumption is generally a function of array size and selector nonlinearity. By considering a generic x bias scheme (where selected and unselected wordlines and unselected and selected bitlines are biased to voltages V, x · V, (1 - x) · V, and ground, respectively) and by employing a mathematical model to accurately estimate the leakage power, we study how the bias scheme can be designed for minimum leakage power consumption for a wide range of array sizes and selector nonlinearities. We demonstrate that the value of factor x that gives minimum power consumption lies somewhere between 1/3 and 1/2.
机译：由于电阻开关存储器的最新发展，交叉点阵列已成为获得高密度存储的一种有吸引力的体系结构。但是，交叉点阵列会遭受偷偷摸摸的电流路径和互连线上的电压降，这可能会导致各种挑战，例如泄漏功率过大，写入失败，写入干扰以及读取余量不足。在本文中，我们将注意力集中在泄漏功耗上。我们证明了使泄漏功耗最小的偏置方案通常是阵列尺寸和选择器非线性的函数。通过考虑通用的x偏置方案（将选定和未选定的字线以及未选定和选定的位线分别偏置到电压V，x·V，（1-x）·V和地），并采用数学模型来准确估算对于漏电功率，我们研究了如何针对多种阵列尺寸和选择器非线性设计偏置方案，以将漏电功耗降至最低。我们证明了给出最小功耗的系数x的值介于1/3和1/2之间。

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