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Low-power approximate MAC unit

机译:低功耗近似MAC单元

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摘要

Sacrificing exact calculations to improve digital circuit performance is at the foundation of approximate computing. In this paper, an approximate multiply-and-accumulate (MAC) unit is introduced. The MAC partial product terms are compressed by using simple OR gates as approximate counters; moreover, to further save energy, selected columns of the partial product terms are not formed. A compensation term is introduced in the proposed MAC, to reduce the overall approximation error. A MAC unit, specialized to perform 2D convolution, is designed following the proposed approach and implemented in TSMC 40nm technology in four different configurations. The proposed circuits achieve power savings more than 60%, compared to standard, exact MAC, with tolerable image quality degradation.
机译:牺牲精确的计算以提高数字电路性能是近似计算的基础。本文介绍了一种近似乘加(MAC)单元。通过使用简单的或门作为近似计数器来压缩MAC部分乘积项;此外,为了进一步节省能量,不形成部分乘积项的选定列。在拟议的MAC中引入了补偿项,以减少整体逼近误差。按照建议的方法设计了专门用于执行2D卷积的MAC单元,并在TSMC 40nm技术中以四种不同的配置实现了该MAC单元。与标准的精确MAC相比,拟议的电路可实现60%以上的功率节省,并且图像质量可容忍下降。

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