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首页> 外文会议>Conference on Ph.D. Research in Microelectronics and Electronics >Low-power optimisation of a pixel array architecture for next generation High Energy Physics detectors
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Low-power optimisation of a pixel array architecture for next generation High Energy Physics detectors

机译：针对下一代高能物理探测器的像素阵列架构的低功耗优化

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A large scale pixel readout chip is being designed by the RD53 Collaboration, in order to prove the suitability of 65 nm technology for the extreme operating conditions foreseen for the High Luminosity upgrades of the ATLAS and CMS experiments at CERN. The use of advanced digital design and simulation tools is essential to guide architectural and implementation choices for the design and optimisation of pixel chips which will be powered from a serial powering scheme. In this work, low power design techniques are reviewed and critically selected based on the requirements of the target application. Chosen techniques are adopted and results of the low power optimisation are presented for a basic unit of the system.
机译：RD53协作设计了大规模像素读数芯片，以证明65nm技术在核心核心天堂和CMS实验的高发光度升级中预见的极端操作条件的适用性。使用先进的数字设计和仿真工具对于指导架构和实现选择来指导架构和实现选择和优化像素芯片的设计和优化，这将由串行电力方案供电。在这项工作中，基于目标应用的要求，对低功率设计技术进行审查和批判性选择。采用所选择的技术，并为系统的基本单元提出了低功耗优化的结果。

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