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Compressive image sensor architecture with on-chip measurement matrix generation

机译：具有片上测量矩阵生成的压缩图像传感器架构

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摘要

A CMOS image sensor architecture that uses a cellular automaton for the pseudo-random compressive sampling matrix generation is presented. The image sensor employs in-pixel pulse-frequency modulation and column wise pulse counters to produce compressed samples. A common problem of compressive sampling applied to image sensors is that the size of a full-frame compressive strategy is too large to be stored in an on-chip memory. Since this matrix has to be transmitted to or from the reconstruction system its size would also prevent practical applications. A full-frame compressive strategy generated using a 1-D cellular automaton showing a class III behavior neither needs a storage memory nor needs to be continuously transmitted. In-pixel pulse frequency modulation and up-down counters allow the generation of differential compressed samples directly in the digital domain where it is easier to improve the required dynamic range. These solutions combined together improve the accuracy of the compressed samples thus improving the performance of any generic reconstruction algorithm.
机译：提出了使用元胞自动机进行伪随机压缩采样矩阵生成的CMOS图像传感器体系结构。图像传感器采用像素内脉冲频率调制和逐列脉冲计数器来产生压缩样本。应用于图像传感器的压缩采样的一个常见问题是，全帧压缩策略的大小太大，无法存储在片上存储器中。由于必须将此矩阵传输到重建系统或从重建系统传输该矩阵，因此其大小也将阻止实际应用。使用显示出III类行为的一维元胞自动机生成的全帧压缩策略既不需要存储内存，也不需要连续传输。像素内脉冲频率调制和上下计数器可直接在数字域中生成差分压缩样本，从而可以更轻松地改善所需的动态范围。这些解决方案结合在一起可以提高压缩样本的准确性，从而提高任何通用重建算法的性能。

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