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A cellular NoC architecture based on butterfly network coding (CBNoC)

机译:基于蝶形网络编码(CBNoC)的蜂窝NoC架构

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The intra-chip communication latency and power consumption become the main bottleneck of the development of multi-core processors. Network-on-Chip (NoC) paradigm is proposed to meet these stringent requirements. Since the wireless network interconnection can achieve high speed data transmission with low power consumption, this paper proposes a cellular NoC architecture based on multiple butterfly network coding clusters with low latency. Data packets and control packets are transmitted on the wireless channel and the wired channel, separately. We also design a Z-X-Y path routing algorithm to achieve the shortest routing. Experiment results prove that, compared with Mesh, the proposed architecture can achieve at least 8% average latency reduction with slight resource increment.
机译:芯片内部的通信等待时间和功耗成为多核处理器发展的主要瓶颈。为了满足这些严格要求,提出了片上网络(NoC)范式。由于无线网络互连可以实现低功耗的高速数据传输,因此本文提出了一种基于低延迟的多个蝶形网络编码簇的蜂窝式NoC架构。数据分组和控制分组分别在无线信道和有线信道上传输。我们还设计了一种Z-X-Y路径路由算法,以实现最短的路由。实验结果证明,与Mesh相比,所提出的体系结构可以在平均资源等待时间增加的情况下将平均等待时间减少至少8%。

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