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Floorplan and placement methodology for improved energy reduction in stacked power-domain design

机译：在堆叠式电源域设计中改善能耗的平面布置图和布局方法

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Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which stacks voltage domains in a design, can effectively improve the power delivery efficiency and thus improve battery lifetime. However, such an approach requires balanced current between different domains across multiple operating scenarios. Furthermore, level shifter insertion (together with shifters' delay impacts), along with placement constraints imposed by power domain regions, can incur power and area penalties. To our knowledge, no existing work performs sub-block-level partitioning optimization for stacked-domain designs. In this paper, we present an optimization framework for stacked-domain designs. Based on an initial placement solution, we apply a flow-based partitioning that is aware of multiple operating scenarios, cell placement, and timing-critical paths to partition cells into two power domains with balanced current and minimized number of inserted level shifters. We further propose heuristics to define regions for each power domain so as to minimize placement perturbation, as well as a dynamic programming-based method to minimize the area cost of power domain generation. In an updated floorplan, we perform matching-based optimization to insert level shifters with minimized wirelength penalty. Overall, our method achieves more than ~10% and 3X battery lifetime improvements in function and sleep modes, respectively.
机译：能量和电池寿命限制是IC设计的关键挑战。在设计中堆叠电压域的堆叠式电源域实现可以有效地提高功率传输效率，从而延长电池寿命。但是，这种方法需要跨多个操作方案在不同域之间平衡电流。此外，电平移位器的插入（以及移位器的延迟影响）以及功率域区域施加的放置限制会招致功率和面积的损失。据我们所知，没有现有的工作可以为堆叠域设计执行子块级分区优化。在本文中，我们提出了一种用于堆叠域设计的优化框架。基于初始放置解决方案，我们应用了基于流的分区，该分区了解多种操作场景，单元放置和对时序要求严格的路径，可将单元划分为两个电源域，且电流均衡且插入的电平移位器数量最少。我们进一步提出启发式方法来定义每个电源域的区域，以最小化放置扰动，以及一种基于动态编程的方法，以最小化电源域生成的面积成本。在更新的平面图中，我们执行基于匹配的优化，以最小化线长损失插入电平转换器。总体而言，我们的方法在功能和睡眠模式下分别实现了约10％以上的电池寿命和3倍的电池寿命改进。

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