Loop aware IR-level annotation framework for performance estimation in native simulation

机译：循环感知的IR级注释框架，用于本机仿真中的性能评估

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Native simulation is an interesting virtual prototyping candidate to speed-up architecture exploration and early software developments. It however does not provide out-of-the box non-functional information needed for software performance estimation. Annotating software with information is complex as highlevel codes and binary codes have different structures due to compiler optimizations. This work proposes an annotation framework at compiler IR-level that focuses on loop structures, and reflects optimizations through a mapping scheme between the binary and the high-level IR. Experiments on instruction count show in average around 2% of error.

机译：本地仿真是一种有趣的虚拟原型候选者，可加快体系结构探索和早期软件开发的速度。但是，它没有提供软件性能评估所需的开箱即用的非功能性信息。由于编译器的优化，高级代码和二进制代码具有不同的结构，因此带有信息的注释软件非常复杂。这项工作提出了一个在编译器IR级别的注释框架，该框架着重于循环结构，并通过二进制和高级IR之间的映射方案反映了优化。关于指令数的实验平均显示出大约2％的错误。

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《Asia and South Pacific Design Automation Conference》|2017年|220-225|共6页
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Omayma Matoussi; Frédéric Pétrot;
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Optimization; Estimation; Binary codes; Computer architecture; Embedded systems; Data mining;

机译：优化;估计;二进制代码;计算机体系结构;嵌入式系统;数据挖掘;

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1. Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation [J] . Matoussi Omayma, Petrot Frederic Integration . 2019,第MARa期

机译：循环感知CFG匹配策略可在IR级本机仿真中准确评估性能
2. Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation [J] . Matoussi Omayma, Petrot Frederic Integration . 2019,第Mara期

机译：循环识别CFG匹配策略，用于IR级原生模拟中的准确性能估算
3. A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design [J] . Daniel Calvo, Pablo Gonzalez, Luis Diaz, Journal of Low Power Electronics . 2011,第1期

机译：用于电源和热感知设计的多处理片上系统本机仿真框架
4. Loop aware IR-level annotation framework for performance estimation in native simulation [C] . Omayma Matoussi, Frédéric Pétrot Asia and South Pacific Design Automation Conference . 2017

机译：循环识别IR级注释框架，用于本机仿真中的性能估计
5. A framework for the design and specification of hard real-time, hardware-in-the-loop simulations of large, avionic systems. [D] . Ricks, Kenneth Gerald. 2002

机译：用于大型航空电子系统的硬实时，硬件在环仿真的设计和规范的框架。
6. Bias optimal linear estimation and the differences between open-loop simulation and closed-loop performance of spiking-based brain-computer interface algorithms [O] . Steven M. Chase, Andrew B. Schwartz, Robert E. Kass -1

机译：偏振最优线性估计和尖锐型脑电脑接口算法开环仿真与闭环性能的差异
7. Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation [O] . Omayma Matoussi, Frédéric Pétrot 2019

机译：循环识别CFG匹配策略，用于IR级原生模拟中的准确性能估算

Loop aware IR-level annotation framework for performance estimation in native simulation

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