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Building energy-efficient multi-level cell STT-RAM caches with data compression

机译：通过数据压缩构建节能的多层单元STT-RAM缓存

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Spin-transfer torque magnetic random access memory (STT-RAM) technology has emerged as a potential replacement of SRAM in cache design, especially for building large-scale and energy-efficient last level caches. Compared with single-level cell (SLC), multi-level cell (MLC) STT-RAM is expected to double cache capacity and increase system performance. However, the two-step read/write access schemes incur considerable energy consumption and performance degradation. In this paper, we propose two techniques using data compression to optimize MLC STT-RAM cache design. The first technique tries to compress a cache line and fit it into only the soft-bit region of the cells, so that reading or writing this cache line takes only one step which is fast and energy-efficient. We introduce a second technique to increase the cache capacity by enabling the left hard-bit region to store another compressed cache line, which can improve the system performance for memory intensive workloads. The experimental results show that, compared with a conventional MLC STT-RAM last level cache design, our overhead minimized technique reduces the dynamic energy consumption by 38.2% on average with the same system performance, and our capacity augmented technique boosts the system performance by 6.1% with 19.2% dynamic energy saving on average, across the evaluated multi-programmed benchmarks.
机译：自旋传递扭矩磁性随机存取存储器（STT-RAM）技术已成为缓存设计中SRAM的潜在替代品，特别是用于构建大规模且节能的末级缓存。与单层单元（SLC）相比，多层单元（MLC）STT-RAM有望使缓存容量增加一倍，并提高系统性能。但是，两步读/写访问方案会导致相当大的能耗和性能下降。在本文中，我们提出了两种使用数据压缩来优化MLC STT-RAM缓存设计的技术。第一种技术试图压缩高速缓存行并将其仅适合于单元的软位区域，以便读取或写入此高速缓存行仅需一步，即快速又节能。我们引入了第二种技术，通过使左侧的硬位区域存储另一条压缩的缓存行来增加缓存容量，从而可以提高内存密集型工作负载的系统性能。实验结果表明，与传统的MLC STT-RAM末级缓存设计相比，我们的开销最小化技术在相同的系统性能下平均可降低38.2％的动态能耗，而容量增强技术可使系统性能提高6.1。在评估的多程序基准中，平均能耗降低了19.2％，而动态能耗平均降低了19.2％。

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