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Efficient circuit failure probability calculation along product lifetime considering device aging

机译：考虑器件老化的有效寿命期间的电路故障概率计算

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A device-aging simulation that efficiently estimates temporal degradation of failure probability of a circuit is proposed. As the size of transistors shrinks, consideration of device aging in addition to manufacturing variability has become an urgent issue for maintaining reliability of LSIs. Contrary to existing techniques that separately handle manufacturing variability and the device aging, we propose a simultaneous evaluation approach using an augmented reliability and subset simulation. By eliminating the repetitive failure-probability calculations at each device-age, the proposed method reduces the number of required circuit simulations to about 1/6 of that of the conventional method without compromising accuracy.
机译：提出了一种器件老化仿真，可以有效地估计电路故障概率的时间退化。随着晶体管的尺寸缩小，除了制造可变性之外，还考虑器件老化的问题已经成为维持LSI的可靠性的紧迫问题。与分别处理制造差异和设备老化的现有技术相反，我们提出了一种使用增强的可靠性和子集仿真的同时评估方法。通过消除每个器件时代的重复故障概率计算，所提出的方法将所需的电路仿真次数减少到传统方法的大约1/6，而不会影响精度。

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