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FFT implementation and optimization on FPGA

机译:FPGA的FFT实现和优化

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摘要

Nowadays, the development of the Fast Fourier Transform (FFT) remains of a great importance due to its substantial role in the field of signal processing and imagery. This latter still attracts the attention of several researchers around the globe. In this paper, an optimized design of the FFT using the radix-2 algorithm, 32 point is proposed. The developed architecture was implemented using an FPGA regarding its flexibility as well as its parallelism and its computational speed. Though, the material resources of the FPGA are limited, particularly the integrated DSP blocks, a new calculation approach was introduced during the VHDL description with the aim to reduce the necessary number of multiplication operation. The experimental validation of the adopted architecture was realized using a Virtex 6, where the numerical synthesis and the post and route described in VHDL was realized using ISE Design Suite 14.7.
机译:如今,由于快速傅里叶变换(FFT)在信号处理和图像领域中的重要作用,其发展仍然非常重要。后者仍然吸引了全球数位研究人员的注意力。本文提出了使用基数为2的32点算法进行FFT的优化设计。关于FPGA的灵活性,并行性和计算速度,开发的体系结构是使用FPGA实现的。尽管FPGA的材料资源有限,特别是集成的DSP模块,但在VHDL描述期间引入了一种新的计算方法,目的是减少必要的乘法运算次数。使用Virtex 6对采用的体系结构进行了实验验证,其中,使用ISE Design Suite 14.7实现了数字综合以及VHDL中描述的发布和路由。

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