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Process Optimization based on the Multi-chip RF Integrated Circuits in System Level Packaging

机译：系统级封装中基于多芯片射频集成电路的工艺优化

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摘要

System-level packaging is one of the most popular sealing and testing technologies in the field of integrated circuits. Using MCM(Multichip Module) technology, analog circuits, digital circuits, memory, power devices, photoelectric devices, microwave devices and various chip components can be effectively assembled in the package body, forming a single semiconductor integrated circuit impossible to complete the multi-functional parts, subsystems or systems. The crosstalk noise between lines can be reduced, and the impedance can be controlled easily and effectively, witch improving the overall performance of integrated circuits. In this paper, process optimization is carried out on the basis of multi-chip system-level integration of conventional process flow. At the same time, the failure mode existing in the process of engineering trial production is simulated to locate the failure cause, so as to ensure product quality and realize industrialization
机译：系统级封装是集成电路领域最流行的密封和测试技术之一。利用MCM（Multichip Module，多芯片模块）技术，可以将模拟电路，数字电路，存储器，功率器件，光电器件，微波器件和各种芯片组件有效地组装在封装体中，从而形成无法完成多功能的单个半导体集成电路。零件，子系统或系统。可以减少线之间的串扰噪声，并且可以容易且有效地控制阻抗，从而改善了集成电路的整体性能。在本文中，工艺优化是在常规工艺流程的多芯片系统级集成的基础上进行的。同时，对工程试生产过程中存在的故障模式进行仿真，找出故障原因，以保证产品质量，实现产业化。

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