This paper presents MOS-NDR, a new prototyping technique for multiple-valued logic circuits combining MOS transistors and multipeak negative differential-resistance (NDR) devices such as resonant-tunneling diodes (RTDs). MOS-NDR emulates the folded current-voltage characteristics of NDR devices such as RTDs using only NMOS transistors, MOS-NDR has enabled the development of a fully integrated multivalued signed-digit full adder (SDFA) circuit by means of a standard 0.6-micron CMOS process technology. The prototype has been fabricated and correct operation has been verified. The circuit dimensions are 123.75 by 38.7 microns, which is more than 15 times smaller than the area required by the equivalent hybrid RTD-CMOS prototype. The propagation delay of the hybrid RTD-CMOS design is estimated to be close to six times higher than that of the MOS-NDR implementation.
展开▼
机译：本文介绍了MOS-NDR，这是一种将MOS晶体管与多峰负差分电阻（NDR）器件（例如谐振隧道二极管（RTD））相结合的多值逻辑电路的原型技术。 MOS-NDR仅使用NMOS晶体管模拟RTD等NDR器件的折叠电流-电压特性，MOS-NDR通过标准的0.6微米技术开发了完全集成的多值有符号数字全加法器（SDFA）电路。 CMOS工艺技术。原型已经制造出来，并且已经验证了正确的操作。电路尺寸为123.75 x 38.7微米，比等效的混合RTD-CMOS原型所需的面积小15倍以上。混合RTD-CMOS设计的传播延迟估计比MOS-NDR实现的传播延迟高近六倍。
展开▼
