An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design, a synchronous version of the algorithm was also designed. The VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercially available tools, the VHDL code was synthesized. After placing and routing, both designs were fabricated with 0.6 /spl mu/m CMOS technology. With a system clock of up to 8 MHz and a power supply of 5 V, the two chips were tested and evaluated, comparing them with the software implementation of the IDEA algorithm. This new approach proves efficiently the lower power consumption of the asynchronous implementation compared to the existing synchronous one. Therefore the asynchronous chip performs efficiently in WEP (Wireless Encryption Protocols) and high speed networks.
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机译：本文介绍了国际数据加密算法（想法）的异步VLSI实现。为了评估异步设计，还设计了算法的同步版本。使用VHDL硬件描述语言以描述算法。通过使用Synopsys商用工具，vhdl代码是合成的。在放置和路由后，两种设计都用0.6 / SPL MU / M CMOS技术制造。通过高达8 MHz的系统时钟和5 V的电源，测试和评估了两个芯片，将它们与思想算法的软件实现进行比较。与现有的同步1相比，这种新方法有效地证明了异步实现的较低功耗。因此，异步芯片在WEP（无线加密协议）和高速网络中有效地执行。
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