The most efficient approach in reducing dynamic power dissipation in digital circuits is to lower the supply voltage. This paper discusses gate-level power optimization through comparing static, non-clocked CMOS logic styles for low-voltage operation. Five promising logic styles were carefully analysed with a testbench to measure propagation delay and power dissipation as a function of supply voltage. The SCMOS logic style has good general characteristics. However, some logic styles, such as DCVSPG, DCVSL, and PPCL, proved to be quite promising in the low voltage region. This clearly suggests that a standard cell library designed for low-power could benefit from the mixed use of different logic styles.
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