Delay estimation of SCL gates with output buffer

机译：带输出缓冲器的SCL门的延迟估计

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A strategy to analytically model propagation delay in CMOS SCL gates with output buffer is proposed. The model is obtained by a suitable linearization of the circuit and assuming a dominant-pole behavior. The delay expressions obtained are related to design and process parameters in a simple way. Since they also have an evident physical meaning, the model allows deep understanding of the SCL circuit behavior, and hence they are helpful in the earliest design phases. The accuracy of the model has been checked by simulating an SCL inverter under various bias and load conditions. The error obtained in realistic cases is lower than 20%.

机译：提出了一种对具有输出缓冲器的CMOS SCL栅极中的传播延迟进行解析建模的策略。该模型是通过对电路进行适当的线性化并假设主极行为来获得的。获得的延迟表达式以简单的方式与设计和过程参数相关。由于它们也具有明显的物理含义，因此该模型可以深入了解SCL电路的行为，因此在最早的设计阶段很有用。通过在各种偏置和负载条件下模拟SCL逆变器来检查模型的准确性。在实际情况下获得的误差低于20％。

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《Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on》|2001年|P.719-722|共4页
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Alioto; M.; Palumbo; G.; Pennisi; S.;
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中图分类无线电电子学、电信技术;
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Delay estimation of SCL gates with output buffer

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