Innovative solutions to enable smaller substrate bump pad size for flip chip technology

机译：创新的解决方案可为倒装芯片技术实现更小的基板凸点焊盘尺寸

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Semiconductor technology is marching towards miniature size, but in contrast requires higher I/Os, which leads to growth in package size and die size for performance enhancement. Therefore the package designer needs to break the conventional design rule and innovate a way to fit more I/Os into the same package/die size, One of the key design rules that fits such criteria is substrate solder resist opening (SRO) design. It is the key element driving the die size and substrate size growth. By optimizing the solder resist opening dimension, the die size can reduce significantly to 15% less. However, when technology pushes the envelop to meet the criteria, a side effect surfaced, which relates to quality and reliability issues. The issues were found at silicon and package integration level. Various options and evaluations were carried out to enable the smaller SRO technology. The success of this project has brought the company significant cost savings for current and future products.

机译：半导体技术正在朝着微型尺寸迈进，但与此相反，它需要更高的I / O，这会导致封装尺寸和管芯尺寸的增长，从而提高性能。因此，封装设计人员需要打破常规的设计规则，并创新一种将更多I / O装入同一封装/管芯尺寸的方法。符合此类标准的关键设计规则之一是衬底阻焊剂开口（SRO）设计。这是驱动芯片尺寸和基板尺寸增长的关键因素。通过优化阻焊剂开口尺寸，可以将管芯尺寸显着减小至15％。但是，当技术推动信封达到标准时，就会出现副作用，这与质量和可靠性问题有关。在芯片和封装集成级别发现了这些问题。为了实现更小的SRO技术，进行了各种选择和评估。该项目的成功为公司节省了当前和未来产品的大量成本。

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《Electronic Components and Technology Conference, 2004. Proceedings. 54th》|2004年|p.1471-1474|共4页
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Cheah Seaw Lai; Ang Toon Yoon; Chen Chee Koang; Singh K.; Earley A.;
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中图分类无线电电子学、电信技术;
关键词
flip-chip devices; integrated circuit packaging; ball grid arrays; voids (solid); circuit optimisation; integrated circuit reliability; FCBGA; die bump voiding defect; substrate bump pad size; flip chip technology; I/O connection number; package size; die size; substrate solder resist opening optimization; package quality; package reliability; silicon integration; package integration; SRO technology;

机译：倒装芯片器件;集成电路封装;球栅阵列;空隙（固体）;电路优化;集成电路可靠性; FCBGA;管芯凸点空洞缺陷;基板凸点焊盘尺寸;倒装芯片技术; I / O连接数;封装尺寸;芯片尺寸;衬底阻焊剂开口优化;封装质量;封装可靠性;硅集成度;封装集成度; SRO技术;

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专利

1. A Visualization-Based Approach for Bump-Pad/IO-Ball Placement and Routing in Flip-Chip/BGA Technology [J] . Albert H. Titus, Bhanu Jaiswal IEEE Transactions on Advanced Packaging . 2006,第3期

机译：倒装芯片/ BGA技术中基于可视化的凹凸焊盘/ IO球布局和布线方法
2. Effect of Migration and Condensation of Pre-existing Voids on Increase in Bump Resistance of Flip Chips on Flexible Substrates during Electromigration [J] . S.W. LIANG, Y.W. CHANG, CHIH CHEN, Journal of Electronic Materials . 2008,第7期

机译：预先存在的空隙的迁移和凝聚对电迁移过程中柔性基板上倒装芯片的抗突点增加的影响
3. Effect of Migration and Condensation of Pre-existing Voids on Increase in Bump Resistance of Flip Chips on Flexible Substrates during Electromigration [J] . S.W. Liang, Y.W. Chang, Chih Chen, Journal of Electronic Materials . 2008,第7期

机译：预先存在的空隙的迁移和凝结对电迁移过程中柔性基板上倒装芯片的抗突点增加的影响
4. Bump non-wet issue in large-die flip chip package with eutectic Sn/Pb solder bump and SOP substrate pad [C] . Xiong Z.P., Ho Pei Sze, Chua K.H. Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th . 2004

机译：具有共晶锡/铅焊料凸点和SOP衬底焊盘的大晶粒倒装芯片封装中的凸点非湿问题
5. Reliability study and technology development of solder-bumped flip chip on low-cost substrate. [D] . Xiao, Guo Wei. 2002

机译：低成本衬底上凸焊倒装芯片的可靠性研究和技术开发。
6. Defect Inspection of Flip Chip Solder Bumps Using an Ultrasonic Transducer [O] . Lei Su, Tielin Shi, Zhensong Xu, 2013

机译：使用超声波传感器检查倒装芯片焊锡凸点的缺陷
7. Peripheral Flip Chip Interconnection on Au Plated Pads using Solder-Capped Cu Pillar Bumps [O] . Hirokazu Noma, Kazushige Toriyama, Keishi Okamoto, 2011

机译：使用焊接Cu柱凸块的Au电镀焊盘上的外围倒装芯片互连

Innovative solutions to enable smaller substrate bump pad size for flip chip technology

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