Implementation of an Arm Compatible Processor Core for SOC Designs

机译：用于SOC设计的Arm兼容处理器内核的实现

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Hardware Description Languages (HDLs) are commonly used to construct hardware systems. Reuse of the design is a common practice to improve the productivity nowadays. In this paper, an implementation of a fully pipelined ARM compatible processor core, which can be embedded into System-on-Chips (SOCs) is presented. The implementation aims to support research, education, and development by opening the source codes. The logic description of the core is based on VHDL. Therefore, the core can be applied to design tools of many vendors and can be easily reused.

机译：硬件描述语言（HDL）通常用于构造硬件系统。重复使用设计是当今提高生产率的一种常见做法。在本文中，提出了一种完全管线化的ARM兼容处理器内核的实现，该处理器内核可以嵌入到片上系统（SOC）中。该实现旨在通过打开源代码来支持研究，教育和开发。内核的逻辑描述基于VHDL。因此，该内核可以应用于许多供应商的设计工具，并且可以轻松地重用。

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《Information and Communications Technology, 2005. Enabling Technologies for the New Knowledge Society: ITI 3rd International Conference on》|2005年|P.851-859|共9页
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Morgan A.A.; Allam M.E.; Salama M.A.; Mansour H.A.K.;
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中图分类工业技术;
关键词
ARM core; IP core-based SOC design; Top-down design; ARM core; IP core-based SOC design; Top-down design;

机译：ARM内核;基于IP内核的SOC设计;自上而下的设计; ARM内核;基于IP内核的SOC设计;自上而下的设计;

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机译：在多核处理器上快速实现与FDTD兼容的格林功能
4. Implementation of an Arm Compatible Processor Core for SOC Designs [C] . Morgan A.A., Allam M.E., Salama M.A., International Conference on Information and Communications Technology . 2005

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Implementation of an Arm Compatible Processor Core for SOC Designs

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