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首页> 外文会议>Information and Communications Technology, 2005. Enabling Technologies for the New Knowledge Society: ITI 3rd International Conference on >Development of a Simultaneously Threaded Multi-Core Processor
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Development of a Simultaneously Threaded Multi-Core Processor

机译：同时线程多核处理器的开发

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Simultaneous Multithreading (SMT) is becoming one of the major trends in the design of future generations of microarchitectures. Its key strength comes from its ability to exploit both thread-level and instruction-level parallelism; it uses hardware resources efficiently. Nevertheless, SMT has its limitations: contention between threads may cause conflicts; lack of scalability, additional pipeline stages, and inefficient handling of long latency operations. Alternatively, Chip Multiprocessors (CMP) are highly scalable and easy to program. On the other hand, they are expensive and suffer from cache coherence and memory consistency problems. This paper proposes a microarchitecture that exploits parallelism at instruction, thread, and processor levels. It merges both concepts of SMT and CMP. Like CMP, multiple cores are used on a single chip. Hardware resources are replicated in each core except for the secondary-level cache which is shared among all cores. The processor applies the SMT technique within each core to make full use of available hardware resources. Moreover, the communication overhead is reduced due to the interdependence between cores. Results show that the proposed microarchitecture outperforms both SMT and CMP. In addition, resources are more evenly distributed among running threads.
机译：同步多线程（SMT）成为下一代微体系结构设计中的主要趋势之一。它的主要优势来自其利用线程级和指令级并行性的能力。它有效地利用了硬件资源。但是，SMT有其局限性：线程之间的争用可能会导致冲突;线程之间的争用可能会导致冲突。缺乏可伸缩性，额外的流水线阶段以及对长等待时间操作的低效率处理。另外，芯片多处理器（CMP）具有高度的可扩展性，并且易于编程。另一方面，它们价格昂贵并且遭受高速缓存一致性和存储器一致性问题的困扰。本文提出了一种微架构，该架构在指令，线程和处理器级别利用并行性。它融合了SMT和CMP的两个概念。与CMP一样，在单个芯片上使用多个内核。硬件资源在每个内核中复制，除了在所有内核之间共享的二级缓存之外。处理器在每个内核中应用SMT技术，以充分利用可用的硬件资源。而且，由于核之间的相互依赖性，减少了通信开销。结果表明，所提出的微体系结构优于SMT和CMP。此外，资源在正在运行的线程之间更均匀地分配。

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