This paper describes an efficient sequential implementation of Advanced Encryption Standard (AES) algorithm on a Field Programmable Gate Arrays (FPGAs) especially targeting it for feedback modes. The design of S-box in the RAM blocks of the devices has resulted in enhanced throughput as well as real estate savings on the development platform. The use of FPGA in cryptographic system has many advantages. Reconfigurable implementation benefit from the hardware based performance of custom VLSI, while maintaining the flexibility of software. With the ever increasing computational power vis-à-vis decreasing costs, reconfigurable devices like FPGAs have become attractive for embedding cryptographic. The throughput of 2.966 Gbps has been achieved with limiting the required area to 481 slices.
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