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首页> 外文会议>ACM/IEEE International Symposium on Low Power Electronics and Design >A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing
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A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing

机译：大规模离散双Vt分配和连续门调整的并行和随机算法

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摘要

We propose a parallel and randomized algorithm to solve the problem of discrete dual-Vt assignment combined with continuous gate sizing which is an important low power design technique in high performance domains. This combinatorial optimization problem is particularly difficult to solve on large-sized circuits. We first introduce a hybrid algorithm which combines the existing heuristics and convex formulations for this problem to achieve a better tradeoff between the runtime of the algorithm and the quality of generated solution. We then extend our algorithm to include parallelism and randomization. We introduce a unique utilization of parallelism to better identify the optimization direction. Consequently, we can reduce both the number of iterations in optimization as well as improve the quality of solution. We further use random sampling to avoid being trapped in local minima and to focus the optimization effort on the more "promising" regions of the solution space. Our algorithm improves the average power by 37% compared to an approach which is based on solving a continuous convex program and applying discretization. Power improvement is over 50% for larger benchmarks for an implementation on a grid of 9 computers.
机译：我们提出了一种并行和随机化算法来解决离散双VT分配的问题与连续栅极尺寸相结合，这是高性能域中的重要低功率设计技术。这种组合优化问题特别难以在大型电路上解决。我们首先介绍一种混合算法，将现有的启发式和凸形配方结合在此问题中，以在算法的运行时间和所生成的解决方案的质量之间实现更好的权衡。然后，我们将算法扩展到包括并行性和随机化。我们介绍了对并行性的独特利用，以更好地识别优化方向。因此，我们可以减少优化中的迭代次数以及提高解决方案的质量。我们进一步使用随机抽样来避免被困在当地最小值中，并将优化努力集中在解决方案空间的“有希望”区域上。与基于求解连续凸面编程并施加离散化的方法相比，我们的算法将平均功率提高了37％。对于9台计算机网格上的实现的较大基准，功率提高超过50％。

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