• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>IEEE international conference on ASIC;ASICON 2009 >High-Speed Reed-Solomon Errors-and-Erasures Decoder Design with Burst Error Correcting
【24h】

High-Speed Reed-Solomon Errors-and-Erasures Decoder Design with Burst Error Correcting

机译：具有突发纠错功能的高速Reed-Solomon纠错和纠删解码器设计

获取原文
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Reed-Solomon code has been extensively studied in both academia and industry for its wide applications in digital communication and data storage systems.However,existing works are focused on errors-alone or errors-and-erasures decoding.In this paper,starting from a recent theoretical work,an efficient VLSI architecture is developed and implemented by exploring pipeline-interleaving inversionless Berlekamp-Massey algorithm,which not only keeps original RS code's error or error-and-erasure correcting capability,but also has significantly improved burst error correcting capacity. The new architecture,denoted as PI-iBM-BEC,is shown to achieve better error correcting capacity and delivers higher throughput with relatively lower hardware complexity compared with prior arts.
机译：Reed-Solomon码在数字通信和数据存储系统中的广泛应用已在学术界和工业界进行了广泛的研究。在最近的理论工作中，通过探索流水线交织的无逆Berlekamp-Massey算法，开发并实现了一种高效的VLSI架构，该算法不仅保留了原始RS码的错误或纠错消除能力，而且还显着提高了突发纠错能力。与现有技术相比，表示为PI-iBM-BEC的新体系结构具有更好的纠错能力，并以相对较低的硬件复杂性提供了更高的吞吐量。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号