Solutions to mitigate parasitic NPN bipolar action in high voltage analog technologies

机译：缓解高压模拟技术中寄生NPN双极作用的解决方案

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This is a study of the parasitic NPN premature turn-on for high voltage BiCMOS technologies. In this work, we will investigate several methods to suppress its turn-on. Using TCAD and TLP we will investigate solutions based on increased well spacing, offset of wells, self-protection and beta reduction through highly doped base implant. We will also investigate the limitations associated with each of these solutions.

机译：这是针对高压BiCMOS技术的寄生NPN过早导通的研究。在这项工作中，我们将研究抑制其开启的几种方法。我们将使用TCAD和TLP研究解决方案，这些解决方案基于增加的阱间距，阱的偏移量，自我保护和通过高掺杂基础注入减少β的方法。我们还将研究与这些解决方案相关的局限性。

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《2010 32nd Electrical Overstress/ Electrostatic Discharge Symposium》|2010年|1-8|共8页
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Salman Akram A; Boselli Gianluca; Kunz Hans; Brodsky Jonathan;
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中图分类电器;
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2. Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect [J] . Karandikar S.K., Sapatnekar S.S. IEEE transactions on very large scale integration (VLSI) systems . 2003,第6期

机译：SOI Domino逻辑的技术映射，并结合了针对寄生双极效应的解决方案
3. Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect [J] . Karandikar S.K., Sapatnekar S.S. IEEE transactions on very large scale integration (VLSI) systems . 2003,第6期

机译：SOI Domino逻辑的技术映射，并结合了针对寄生双极效应的解决方案
4. Solutions to mitigate parasitic NPN bipolar action in high voltage analog technologies [C] . Salman Akram A, Boselli Gianluca, Kunz Hans, 2010 32nd Electrical Overstress/ Electrostatic Discharge Symposium . 2010

机译：缓解高压模拟技术中寄生NPN双极作用的解决方案
5. InP-based NPN and PNP heterojunction bipolar transistor design, technology, and characterization for enhanced high-frequency power amplification. [D] . Sawdai, Donald James. 1999

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8. Approximate HSPICE model for orbit low noise analog bipolar NPN transistors [R] . Zimmerman, T. 1991

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Solutions to mitigate parasitic NPN bipolar action in high voltage analog technologies

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