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首页> 外文会议>2011 International Conference on Embedded Computer Systems : Architectures, Modeling and Simulation >On-chip dynamic programming networks using 3D-TSV integration
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On-chip dynamic programming networks using 3D-TSV integration

机译：使用3D-TSV集成的片上动态编程网络

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Recent technological advances in three-dimensional (3D) semiconductor fabrication have provided a promising platform for realizing densely interconnected multicore, multiprocessor, and networks-on-chip (NoC) based systems. As the on-chip complexity grows significantly with the number of computational, control, and communication units, design considerations and the provision for efficient run-time resources management in large-scale system becomes critical. We have developed an on-chip distributed dynamic-programming (DP) network [3] [5] for a range of applications including optimal paths planning [6], dynamic routing [5] and deadlock detection [2]. This paper presents a design of DP-network, implemented in a fully stacked 3-layer three-dimensional (3D) through-silicon via (TSV) 150 nm CMOS technology through MIT Lincoln Lab [1]. The vertical inter-unit communication is achieved by means of TSV, and the mesh interconnection provides a natural minimal area overhead associated with this communication. The prototype circuit measures 2mm×2mm. Test results demonstrated the effectiveness of such a DP-network for deadlock detection and the computational delay is less than 9 ns for detecting deadlock from a large-scale network. This work provides promising results for future networks-on-chip application using 3D embedded DP-network.
机译：三维（3D）半导体制造中的最近技术进步已经为实现密集的互连的多核，多处理器和基于网络（NOC）的系统提供了有希望的平台。随着片上复杂性随着计算，控制和通信单元的数量而大大增长，大规模系统中的设计考虑因素和有效的运行时间资源管理的规定变得至关重要。我们开发了一种片上分布式动态编程（DP）网络[3] [5]，包括一系列应用程序，包括最佳路径规划[6]，动态路由[5]和死锁检测[2]。本文介绍了DP网络的设计，通过MIT LICOLN LAB [1]在完全堆叠的3层三维（3D）通过 - 硅通孔（TSV）150nm CMOS技术中实现。通过TSV实现垂直间通信，并且网格互连提供与该通信相关的自然最小区域开销。原型电路尺寸为2mm×2mm。测试结果证明了这种DP网络的有效性，用于死锁检测，并且计算延迟小于9 ns，用于检测来自大型网络的死锁。这项工作为使用3D嵌入式DP-Network提供了未来的芯片应用程序的有希望的结果。

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