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High level quantitative hardware prediction modeling using statistical methods

机译:使用统计方法的高级定量硬件预测建模

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With the increasing proliferation of heterogeneous and reconfigurable computing, it has become essential to have efficient prediction models to drive early HW-SW partitioning and co-design. In this paper, we present a high level quantitative prediction modeling approach that accurately models the relation between hardware and software metrics, based on several statistical techniques. The proposed approach generates models that predict hardware performance indicators for reconfigurable components, such as the number of slices, the number of flip-flops, and the number of wires. It utilizes automatic model selection, artificial neural networks, (logistic) regression, and data transformations. These models take a high-level language description as input, enabling hardware prediction in the early design stages. We calibrate the models for two sets of tools targeting Xilinx and Altera FPGAs, where we report, for example, and error of 14% for the number of multipliers in case of Xilinx and an error of only 18% for the number of wires in case of Altera. To provide a realistic evaluation, we validate the approach using 181 kernels, contrary to the majority of the existing techniques, which use libraries of tens of kernels at most.
机译:随着异构和可重构计算的不断增长,拥有有效的预测模型来驱动早期的硬件-软件分区和协同设计已变得至关重要。在本文中,我们基于几种统计技术,提出了一种高级定量预测建模方法,该方法可以准确地对硬件和软件指标之间的关系进行建模。所提出的方法生成的模型可以预测可重新配置组件的硬件性能指标,例如切片数量,触发器数量和导线数量。它利用自动模型选择,人工神经网络,(逻辑)回归和数据转换。这些模型将高级语言描述作为输入,从而可以在设计的早期阶段进行硬件预测。我们校准了针对Xilinx和Altera FPGA的两组工具的模型,例如,在Xilinx情况下,我们报告的乘法器数量误差为14%,在情况下为线数误差仅为18%的Altera。为了提供现实的评估,我们使用181个内核来验证该方法,这与大多数现有技术(最多使用数十个内核的库)相反。

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