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SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

机译：SLD-1（静音大数据路径）：超低功耗可重构加速器

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SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm × 4.2mm 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage scaling.

机译：SLD（Silent Large Datapath）-1是用于媒体处理的原型加速器，它由一个大型处理单元（PE）阵列组成，该阵列包括带组合电路的24位8×8 PE和一个用于访问数据存储器的小型微控制器。它采用2.1mm×4.2mm 65 nm CMOS制成，通过减少时钟树的开销和电压缩放的好处，实现了1.356GOPS / 11mW的持续性能。

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《2011 IEEE Cool Chips XIV》|2011年|p.1-3|共3页
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作者
Ozaki Nobuaki; Usami Kimiyoshi; Amano Hideharu; Namiki Mitaro; Nakamura Hiroshi; Kondo Masaaki;
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正文语种
中图分类微电子学、集成电路（IC）;
关键词
65nmCMOS; Low Power; Reconfigurable System;

机译：65nmCMOS;低功耗;可重构系统;

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专利

1. Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips [J] . Ozaki Nobuaki, Yasuda Yoshihiro, Izawa Mai, Micro, IEEE . 2011,第6期

机译：超大型阵列：超低功耗可重构加速器芯片
2. CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks [J] . Saha Saunak, Duwe Henry, Zambreno Joseph Journal of VLSI signal processing systems for signal, image, and video technology . 2020,第9期

机译：Cynnapse：用于尖峰神经网络的低功耗可重构神经推理加速器
3. UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Accelerator for Efficient Keyword Spotting [J] . Bernardo Paul Palomero, Gerum Christoph, Frischknecht Adrian, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2020,第11期

机译：UltraTrail：可配置的UltraLow-Power TC-Reset AI加速器，用于高效关键字斑点
4. SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator [C] . Ozaki Nobuaki, Usami Kimiyoshi, Amano Hideharu, IEEE Symposium on Low-Power and High-Speed Chips . 2011

机译：SLD-1（静音大型数据路径）：超低功率可重新配置加速器
5. Ultra-dynamic Fine-grained Power and Clock Management Techniques for Microprocessors and Machine Learning Accelerators [D] . Jia, Tianyu . 2019

机译：用于微处理器和机器学习加速器的超动态细粒型电力和时钟管理技术
6. Medlay: A Reconfigurable Micro-Power Management to Investigate Self-Powered Systems [O] . Jan Kokert, Tobias Beckedahl, Leonhard M. Reindl 2018

机译：Medlay：可重新配置的微功率管理用于研究自供电系统
7. A Low-Power Reconfigurable Datapath for Advanced Speech Coding Algorithms [O] . Konstantinos Katsoulakis, Tony Kirkham, Sami Khawam 2015

机译：用于高级语音编码算法的低功耗可重配置数据通路

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

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